TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 109

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

Preliminary Data Sheet
October 2000
JTAG Boundary-Scan Specification
Instruction Register
The instruction register (IR) is 4 bits in length. Table 49 shows the BS instructions implemented by the
TFRA08C13.
Table 49. TFRA08C13’s Boundary-Scan Instructions
The instructions not supported in TFRA08C13 are
INTEST, RUNBIST, TOGGLE. A fixed binary 0001 pat-
tern (the 1 into the least significant bit) is loaded into
the IR in the capture-IR controller state. The IDCODE
instruction (binary 0001) is loaded into the IR during
the test-logic-reset controller state and at powerup.
The following is an explanation of the instructions sup-
ported by TFRA08C13 and their effect on the devices'
pins.
EXTEST
This instruction enables the path cells, the pins of the
ICs, and the connections between ASICs to be tested
via the circuit board. The test data can be loaded in the
chosen position of the BS register by means of the
SAMPLE/PRELOAD instruction. The EXTEST instruc-
tion selects the BS register as the test data register.
The data at the function inputs is clocked into the BS
register on the rising edge of TCK in the CAPTURE-DR
state. The contents of the BS register can be clocked
out via TDO in the SHIFT-DR state. The value of the
function outputs is solely determined by the contents of
the data clocked into the BS register and only changes
in the UPDATE-DR state on the falling edge of TCK.
Lucent Technologies Inc.
Lucent Technologies Inc.
EVERYTHING ELSE
SAMPLE/PRELOAD
Instruction
EXTEST
IDCODE
BYPASS
HIGHZ
Code
0000
0001
0100
0101
1111
—
Boundary Scan
Boundary Scan
Act. Register
Identification
TDI TDO
BYPASS
BYPASS
BYPASS
(continued)
NORMAL
NORMAL
NORMAL
Mode
TEST
X
X
DCODE
Information regarding the manufacturer’s ID for Lucent,
the IC number, and the version number can be read out
serially by means of the IDCODE instruction. The
IDCODE register is selected, and the BS register is set
to normal mode in the UPDATE-IR state. The IDCODE
is loaded at the rising edge of TCK in the CAPTURE-
DR state. The IDCODE register is read out via TDO in
the SHIFT-DR state.
HIGHZ
All 3-statable outputs are forced to a high-impedance
state, and all bidirectional ports to an input state by
means of the HIGHZ instruction. The impedance of the
outputs is set to high in the UPDATE-IR state. The func-
tion outputs are only determined in accordance with
another instruction if a different instruction becomes
active in the UPDATE-IR state. The BYPASS register is
selected as the test data register. The HIGHZ instruc-
tion is implemented in a similar manner to that used for
the BYPASS instruction.
SAMPLE/PRELOAD
The SAMPLE/PRELOAD instruction enables all the
input and output pins to be sampled during operation
(SAMPLE) and the result to be output via the shift
chain. This instruction does not impair the internal logic
functions. Defined values can be serially loaded in the
BS cells via TDI while the data is being output (PRE-
LOAD).
Min. shift path
Test external
Read Manuf.
Sample/load
connections
Function
Register
3-state
TFRA08C13 OCTAL T1/E1 Framer
—
Output—High Impedance
Output—High Impedance
Output Defined Via
BS Register
Core Logic
Core Logic
Core Logic
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