TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 50

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

TFRA08C13 OCTAL T1/E1 Framer
Frame Formats
The CRC-4 word, located in submultiframe N, is the
remainder after multiplication by x
(modulo 2) by the generator polynomial x
the polynomial representation of the submultiframe N –
1. Representing the contents of the submultiframe
check block as a polynomial, the first bit in the block,
i.e., frame 0, bit 1 or frame 8, bit 1, is taken as being the
most significant bit and the least significant bit in the
check block is frame 7 or frame 15, bit 256. Similarly,
C
remainder and C
der. The encoding procedure, as described in ITU Rec.
G.704 Section 2.3.3.5.2, follows:
The decoding procedure, as described in ITU Rec.
G.704 Section 2.3.3.5.3, follows:
50
1
The CRC-4 bits in the SMF are replaced by binary
0s.
The SMF is then acted upon the multiplication/divi-
sion process referred to above.
The remainder resulting from the multiplication/divi-
sion process is stored, ready for insertion into the
respective CRC-4 locations of the next SMF.
A received SMF is acted upon by the multiplication/
division process referred to above, after having its
CRC-4 bits extracted and replaced by 0s.
The remainder resulting from this division process is
then stored and subsequently compared on a bit-by-
bit basis with the CRC bits received in the next SMF.
If the remainder calculated in the decoder exactly
corresponds to the CRC-4 bits received in the next
SMF, it is assumed that the checked SMF is error-
free.
is defined to be the most significant bit of the
4
the least significant bit of the remain-
(continued)
4
and then division
4
+ x + 1, of
CEPT Loss of CRC-4 Multiframe Alignment
(LTS0MFA)
Loss of basic frame alignment forces the receive framer
into a loss of CRC-4 multiframe alignment state. This
state is reported by way of the status registers
FRM_SR1 bit 2. Once basic frame alignment is
achieved, a new search for CRC-4 multiframe align-
ment is initiated. During a loss of CRC-4 multiframe
alignment state the following occurs:
The CRC-4 error counter is halted.
The CRC-4 error monitoring circuit for errored sec-
onds and severely errored seconds is halted.
The received E-bit counter is halted.
The received E-bit monitoring circuit for errored sec-
onds and severely errored seconds at the remote
end interface is halted.
Receive continuous E-bit monitoring is halted.
All receive Sa6 code monitoring and counting func-
tions are halted.
The updating of the receive Sa stack is halted and
the receive Sa stack interrupt is deactivated.
Optionally, A = 1 may be automatically transmitted to
the line if register FRM_PR27 bit 2 is set to 1.
Optionally, E = 0 may be automatically transmitted to
the line if register FRM_PR28 bit 4 is set to 1.
Optionally, if LTS0MFA monitoring in the perfor-
mance counters is enabled, by setting registers
FRM_PR14 through FRM_PR17 bit 1 to 1, then
these counts are incremented once per second for
the duration of the LTS0MFA state.
Preliminary Data Sheet
Lucent Technologies Inc.
Lucent Technologies Inc.
October 2000