TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 141

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

Preliminary Data Sheet
October 2000
Lucent Technologies Inc.
Lucent Technologies Inc.
Framer Register Architecture
Receive Signaling Registers: CEPT Format
Table 105. Receive Signaling Registers: CEPT Format (FRM_RSR0—FRM_RSR31) (Y40—Y5F)
* In PSCO or PSC1 signaling mode, this bit is undefined.
Framer Parameter/Control Registers
Registers FRM_PR0—FRM_PR70 define the mode configuration of each framer. All are read/write registers.
These registers are initially set to a default value upon a hardware reset, which is indicated in the register definition.
Interrupt Group Enable Registers (FRM_PR0—FRM_PR7)
The bits in this register group enable the status registers FRM_SR0—FRM_SR7 to assert the interrupt pin. The
default value of these registers is 00 (hex).
FRM_PR0 is the primary interrupt group enable register which enables the event groups in interrupt status register
FRM_SR0. A bit set to 1 in this register enables the corresponding bit in the interrupt status register FRM_SR0 to
assert the interrupt pin.
FRM_PR1—FRM_PR7 are the secondary interrupt enable registers. A bit set to 1 in these registers enables the
corresponding bit in the status register to assert the interrupt pin.
Table 106. Summary of Interrupt Group Enable Registers (FRM_PR0—FRM_PR7) (Y60—Y67)
FRM_RSR1—FRM_RSR15
FRM_RSR[17:31]
Parameter/
Register
FRM_PR0
FRM_PR1
FRM_PR2
FRM_PR3
FRM_PR4
FRM_PR5
FRM_PR6
FRM_PR7
Control
Receive Signal Registers
Register
Enabled
FRM_SR0
FRM_SR1
FRM_SR2
FRM_SR3
FRM_SR4
FRM_SR5
FRM_SR6
FRM_SR7
Status
FDL_LLBOFF
NTREUAS
ETREUAS
Register
(TSaSR)
RQUASI
RSa6=F
Status
S96SR
SLIPU
Bit 7
AIS
FDL_LLBON
Bit 7
RPSUEDO
ETRESES
NTRESES
Register
Reserved
(RSaSR)
RSa6=E
Status
P
P
SLIPO
AUXP
Bit 6
(continued)
Bit 6—5
FDL_PLBOFF
LCRCATMX
( SLC TFSR)
RTS16AIS
NTREBES
PTRNBER
ETREBES
Register
X
X
RSa6=C
Status
RSSFE
Bit 5
E[17:31]
E[1:15]
Bit 4
FDL_PLBON
( SLC RFSR)
Register
ETREES
NTREES
DETECT
RSa6=A
Status
TSSFE
REBIT
LBFA
Bit 4
*
D[17:31] C[17:31]
D[1:15]
Bit 3
TFRA08C13 OCTAL T1/E1 Framer
FRM_SR7)
FRM_SR5,
FRM_SR6,
Register
NROUAS
RSa6=8
ETUAS
NTUAS
Status
LLBON
LFALR
(CMA)
Bit 3
(read
ESE
ECE
and
C[1:15]
Bit 2
(LTS0MFA)
FRM_SR4)
NT1OUAS
FRM_SR3
Register
LLBOFF
CREBIT
Status
ETSES
NTSES
LTSFA
CRCE
(BFA)
Bit 2
(read
FAE
and
B[17:31]
B[1:15]
Bit 1
(RTS16MFA)
(LTS16MFA)
FRM_SR2)
Register
EROUAS
NTBES
Status
ETBES
LSFA
RJYA
SSFA
Bit 1
(read
RAC
FBE
A[17:31]
A[1:15]
Bit 0
FRM_SR1)
Register
Status
OUAS
ETES
NTES
Bit 0
(read
FAC
RFA
LFV
CFA
LFA
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