TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 84

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

TFRA08C13 OCTAL T1/E1 Framer
Facility Data Link
Data may be extracted from and inserted into the facility data link in SLC -96, DDS, ESF, and CEPT framing for-
mats. In CEPT, any one of the Sa bits can be declared as the facility data link by programming register FRM_PR43
bit 0—bit 2. Access to the FDL is made through:
In the ESF frame format, automatic assembly and
transmission of the performance report message
(PRM) as defined in both ANSI T1.403-1995 and Tel-
cordia Technologies * TR-TSY-000194 Issue 1, 12—87
is managed by the receive framer and transmit FDL
sections. The ANSI T1.403-1995 bit-oriented data link
messages (BOM) can be transmitted by the transmit
FDL section and recognized and stored by the receive
FDL section.
Receive Facility Data Link Interface
Summary
A brief summary of the receive facility data link func-
tions is given below:
84
The FDL pins (RFDL, RFDLCK, TFDL, and TFDLCK). Figure 15 shows the timing of these signals.
The 64-byte FIFO of the FDL HDLC block. FDL information passing through the FDL HDLC Section may be
framed in HDLC format or passed through transparently.
RFDLCK
Bit-oriented message (BOM) operation. The ANSI
T1.403-1995 bit-oriented data link messages are
recognized and stored in register FDL_SR3. The
number of times that an ANSI code must be received
for detection can be programmed from 1 to 10 by
TFDLCK
Figure 31. TFRA08C13 Facility Data Link Access Timing of the Transmit and Receive Framer Sections
RFDL
TFDL
t11
t8
t10
t9
t9
*
Telcordia Technologies is a registered trademark of Bell
Communications Research, Inc.
writing to register FDL_PR0 bit 4— bit 7. When a
valid ANSI code is detected, register FDL_SR0 bit 7
(FRANSI) is set.
HDLC operation. This is the default mode of opera-
tion when the FDL receiver is enabled (register
FDL_PR1 bit 2 = 1). The HDLC framer detects the
HDLC flags, checks the CRC bytes, and stores the
data in the FDL receiver FIFO (register FDL_SR4)
along with a status of frame (SF) byte.
HDLC operation with performance report mes-
sages (PRM). This mode is enabled by setting regis-
ter FDL_PR1 bit 2 and bit 6 to 1. In this case, the
receive FDL will store the 13 bytes of the PRM report
field in the FDL receive FIFO (register FDL_SR4)
along with a status of frame (SF) byte.
Transparent operation. Enabling the FDL and set-
ting register FDL_PR9 bit 6 (FTM) to 1 disables the
HDLC processing. Incoming data link bits are stored
in the FDL receive FIFO (register FDL_SR4).
t8: TFDLCK CYCLE =
t9: TFDL TO TFDLCK SETUP/HOLD = 40 ns
t10: RFDLCK CYCLE =
t11: RFDLCK TO RFDL DELAY = 40 ns
Preliminary Data Sheet
Lucent Technologies Inc.
Lucent Technologies Inc.
125 s (DDS)
250 s (ALL OTHER
MODES)
October 2000
125 s (DDS)
250 s (ALL OTHER
MODES)
5-3910(F).cr.1