MT55L256L36P MICRON [Micron Technology], MT55L256L36P Datasheet - Page 10

• Manufacturer Part Number: MT55L256L36P
• Description: 8Mb ZBT SRAM
• Manufacturer: MICRON [Micron Technology]

FBGA PIN DESCRIPTIONS (CONTINUED)
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
4E, 4F, 4G, 4H, 4E, 4F, 4G, 4H,
7N, 8D, 8E, 8F, 7N, 8D, 8E, 8F,
10L, 10M, 11D 10L, 10M, 11J,
4J, 4K, 4L, 4M, 4J, 4K, 4L, 4M,
3C, 3D, 3E, 3F, 3C, 3D, 3E, 3F,
3G, 3J, 3K, 3L, 3G, 3J, 3K, 3L,
(b)
11E, 11F, 11G 11K, 11L, 11M
(a)
3M, 3N, 9C,
1H, 2H, 4D,
9L, 9M, 9N
2G, 1J, 1K,
8K, 8L, 8M
9D, 9E, 9F,
9G, 9J, 9K,
8G,8H, 8J,
2D, 2E, 2F,
1L, 1M
10J, 10K,
x18
11C
1N
8A
8B
1R
–
–
10F, 10G, 11D,
11E, 11F, 11G
(d)
(c)
(b)
(a)
3M, 3N, 9C,
1H, 2H, 4D,
1G, 2D, 2E,
1M, 2J, 2K,
9L, 9M, 9N
8K, 8L, 8M
9D, 9E, 9F,
9G, 9J, 9K,
8G,8H, 8J,
x32/x36
1D, 1E, 1F,
2F, 2G,
2L, 2M
1J, 1K, 1L,
10D, 10E,
10J, 10K,
11N
11C
1N
8A
1C
8B
1R
SYMBOL
NF/DQPb
NF/DQPd
NF/DQPa
ADV/LD#
NF/DQPc
(LBO#)
MODE
V
DQb
DQd
DQa
DQc
OE#
(G#)
V
DD
DD
Q
Output DQa’s; Byte “b” is associated with DQb’s. For the x32 and x36
Supply Power Supply: See DC Electrical Characteristics and Operating
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated with
TYPE
Input
Input
Input
NF/
I/O
(continued on next page)
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
Synchronous Address Advance/Load: When HIGH, this input is used
to advance the internal burst counter, controlling burst access after
the external address is loaded. When ADV/LD# is HIGH, R/W# is
ignored. A LOW on ADV/LD# clocks a new address at the CLK rising
edge.
Mode: This input selects the burst sequence. A LOW on this input
selects “linear burst.” NC or HIGH on this input selects “interleaved
burst.” Do not alter input state while device is operating.
versions, Byte “a” is associated with DQa’s; Byte “b” is associated
with DQb’s; Byte “c” is associated with DQc’s; Byte “d” is associated
with DQd’s. Input data must meet setup and hold times around the
rising edge of CLK.
No Function/Parity Data I/Os: On the x32 version, these are No
Function(NF). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
Conditions for range.
Operating Conditions for range.
10
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
PIPELINED ZBT SRAM
©2001, Micron Technology, Inc.