MT55L256L36P MICRON [Micron Technology], MT55L256L36P Datasheet - Page 3

• Manufacturer Part Number: MT55L256L36P
• Description: 8Mb ZBT SRAM
• Manufacturer: MICRON [Micron Technology]

GENERAL DESCRIPTION
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
256K x 32, or 256K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. These SRAMs are optimized for 100 percent
bus utilization, eliminating any turnaround cycles for
READ to WRITE, or WRITE to READ, transitions. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
The synchronous inputs include all addresses, all data
inputs, chip enable (CE#), two additional chip enables
for easy depth expansion (CE2, CE2#), cycle start input
(ADV/LD#), synchronous clock enable (CKE#), byte
write enables (BWa#, BWb#, BWc#, and BWd#), and
read/write (R/W#).
(OE#, which may be tied LOW for control signal mini-
mization), clock (CLK), and snooze enable (ZZ, which
may be tied LOW if unused). There is also a burst mode
pin (MODE) that selects between interleaved and linear
burst modes. MODE may be tied HIGH, LOW, or left
unconnected if burst is unused. The data-out (Q),
enabled by OE#, is registered by the rising edge of CLK.
WRITE cycles can be from one to four bytes wide as
controlled by the write control inputs.
ated by the ADV/LD# input. Subsequent burst
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
The Micron
Micron’s 8Mb ZBT SRAMs integrate a 512K x 18,
Asynchronous inputs include the output enable
All READ, WRITE, and DESELECT cycles are initi-
®
Zero Bus Turnaround
™
(ZBT
®
) SRAM
3
addresses can be internally generated as controlled by
the burst advance pin (ADV/LD#). Use of burst mode
is optional. It is allowable to give an address for each
individual READ and WRITE cycle. BURST cycles wrap
around after the fourth access from a base address.
bus, the pipelined ZBT SRAM uses a LATE LATE WRITE
cycle. For example, if a WRITE cycle begins in clock cycle
one, the address is present on rising edge one. BYTE
WRITEs need to be asserted on the same cycle as the
address. The data associated with the address is required
two cycles later, or on the rising edge of clock cycle three.
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes to
be written. During a BYTE WRITE cycle, BWa# controls
DQa pins; BWb# controls DQb pins; BWc# controls
DQc pins; and BWd# controls DQd pins. Cycle types
can only be defined when an address is loaded, i.e.,
when ADV/LD# is LOW. Parity/ECC bits are only
available on the x36 version.
power supply, and all inputs and outputs are LVTTL-
compatible. Users can choose either a 2.5V or 3.3V I/O
version. The device is ideally suited for systems requir-
ing high bandwidth and zero bus turnaround delays.
datasheets) for the latest data sheet.
To allow for continuous, 100 percent use of the data
Address and write control are registered on-chip to
Micron’s 8Mb ZBT SRAMs operate from a +3.3V V
Please refer to Micron’s Web site
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PIPELINED ZBT SRAM
(www.micron.com/
©2001, Micron Technology, Inc.
DD