MT55L256L36P MICRON [Micron Technology], MT55L256L36P Datasheet - Page 18

• Manufacturer Part Number: MT55L256L36P
• Description: 8Mb ZBT SRAM
• Manufacturer: MICRON [Micron Technology]

TRUTH TABLE
(Notes 5-10)
NOTE: 1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
O P E R A T I O N
DESELECT Cycle
DESELECT Cycle
DESELECT Cycle
CONTINUE DESELECT Cycle
READ Cycle
(Begin Burst)
READ Cycle
(Continue Burst)
NOP/DUMMY READ
(Begin Burst)
DUMMY READ
(Continue Burst)
WRITE Cycle
(Begin Burst)
WRITE Cycle
(Continue Burst)
NOP/WRITE ABORT
(Begin Burst)
WRITE ABORT
(Continue Burst)
IGNORE CLOCK EDGE
(Stall)
SNOOZE MODE
10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth burst cycle.
11. The address counter is incremented for all CONTINUE BURST cycles.
2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation.
3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off
4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it
5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#,
6. BWa# enables WRITEs to Byte “a” (DQa pins); BWb# enables WRITEs to Byte “b” (DQb pins); BWc# enables WRITEs to
7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
8. Wait states are inserted by setting CKE# HIGH.
9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle
is executed first.
A WRITE ABORT means a WRITE command is given, but no operation is performed.
the output drivers during a WRITE cycle. OE# may be used when the bus turn-on and turn-off times do not meet an
application’s requirements.
occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE
CLOCK EDGE cycle.
BWc# and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW.
Byte “c” (DQc pins); BWd# enables WRITEs to Byte “d” (DQd pins).
ADDRESS
External
External
External
Current
U S E D
None
None
None
None
None
None
Next
Next
Next
Next
C E # CE2# C E 2 Z Z
H
X
X
X
X
L
X
L
X
L
X
L
X
X
H
X
X
X
X
X
X
L
X
X
X
L
L
L
H
H
H
H
X
X
X
X
X
X
X
X
X
L
18
H
L
L
L
L
L
L
L
L
L
L
L
L
L
ADV/
L D # R / W # B W x O E # C K E # C L K
H
H
H
H
H
X
X
L
L
L
L
L
L
L
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
X
X
X
H
H
X
X
X
L
X
L
X
X
H
X
X
X
X
X
X
X
H
X
X
X
L
L
PIPELINED ZBT SRAM
H
H
X
X
X
X
X
X
X
X
X
X
L
L
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H
L-H
L-H High-Z
L-H
L-H
L-H High-Z
L-H
L-H High-Z
L-H High-Z
X
High-Z
©2001, Micron Technology, Inc.
D Q
Q
Q
D
D
–
N O T E S
1, 11
3, 11
1, 2,
1, 3,
1, 2,
2, 3
11
11
1
2
3
4