MT55L256L36P MICRON [Micron Technology], MT55L256L36P Datasheet - Page 22

• Manufacturer Part Number: MT55L256L36P
• Description: 8Mb ZBT SRAM
• Manufacturer: MICRON [Micron Technology]

FBGA THERMAL RESISTANCE
AC ELECTRICAL CHARACTERISTICS
(Notes 2, 3, 4) (0°C ≤ T
NOTE: 1. This parameter is sampled.
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
DESCRIPTION
Junction to Ambient
(Airflow of 1m/s)
Junction to Case (Top)
Junction to Pins (Bottom)
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
Address
Clock enable (CKE#)
Control signals
Data-in
Hold Times
Address
Clock enable (CKE#)
Control signals
Data-in
10. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
11. Preliminary package data.
2. OE# can be considered a “Don’t Care” during WRITEs; however, controlling OE# can help fine-tune a system for
3. Test conditions as specified with output loading as shown in Figure 1 for 3.3V I/O (V
4. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is
5. Measured as HIGH above V
6. Refer to Technical Note TN-55-01, “Designing with ZBT SRAMs,” for a more thorough discussion on these parameters.
7. This parameter is sampled.
8. This parameter is measured with output loading as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
9. Transition is measured ±200mV from steady state voltage.
turnaround timing.
Figure 3 for 2.5V I/O (V
defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.
when they are being registered into the device. All other synchronous inputs must meet the setup and hold times
with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each
rising edge of CLK when ADV/LD# is LOW to remain enabled.
A
≤ +70°C; V
DD
Test conditions follow standard test methods
Q = +2.5V +0.4V/-0.125V).
IH
and procedures for measuring thermal
DD
and LOW below V
= +3.3V ±0.165V unless otherwise noted)
impedance, per EIA/JESD51.
SYMBOL
t
t
t
t
KHQX1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
KHKH
KHQV
KHQX
AVKH
DVKH
KHAX
KHDX
KHQZ
GLQV
GLQX
GHQZ
CVKH
KHCX
KHKL
KLKH
EVKH
KHEX
f
KF
CONDITIONS
IL
.
MIN
6.0
1.7
1.7
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0
22
-6
MAX
166
3.5
3.5
3.5
3.5
8Mb: 512K x 18, 256K x 32/36
MIN
7.5
2.0
2.0
1.5
1.5
1.5
1.7
1.7
1.7
1.7
0.5
0.5
0.5
0.5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
-7.5
MAX
133
4.2
3.5
4.2
4.2
PIPELINED ZBT SRAM
SYMBOL
θ
θ
θ
DD
JA
JC
JB
MIN
3.2
3.2
1.5
1.5
1.5
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
10
Q = +3.3V ±0.165V) and
0
-10
TYP
MAX
40
17
9
100
5.0
3.5
5.0
5.0
UNITS
©2001, Micron Technology, Inc.
UNITS NOTES
MHz
°C/W
°C/W
°C/W
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6, 7, 8, 9
6, 7, 8, 9
6, 7, 8, 9
6, 7, 8, 9
NOTES
1, 11
1, 11
1, 11
10
10
10
10
10
10
10
10
5
5
6
2