MT55L256L36P MICRON [Micron Technology], MT55L256L36P Datasheet - Page 9

• Manufacturer Part Number: MT55L256L36P
• Description: 8Mb ZBT SRAM
• Manufacturer: MICRON [Micron Technology]

FBGA PIN DESCRIPTIONS
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
11A, 2B, 10B,
2A, 9A, 10A, 2A, 9A, 10A,
9P, 10P, 3R,
4R, 8R, 9R,
3P, 4P, 8P,
10R, 11R
x18
11H
6R
5B
4A
7A
7B
6B
3A
6A
3B
6P
–
–
9P, 10P, 3R,
4R, 8R, 9R,
3P, 4P, 8P,
10R, 11R
x32/x36
2B, 10B,
11H
5A
4A
7A
3A
6A
6R
5B
4B
7B
6B
3B
6P
SYMBOL
BWa#
BWb#
BWd#
BWc#
CKE#
R/W#
CE2#
SA1
SA0
CLK
CE#
CE2
SA
ZZ
TYPE
Input Synchronous Address Inputs: These inputs are registered and
Input Synchronous Byte Write Enables: These active LOW inputs allow
Input Synchronous Clock Enable: This active LOW input permits CLK to
Input Read/Write: This input determines the cycle type when ADV/LD#
Input Clock: This signal registers the address, data, chip enable, byte
Input Synchronous Chip Enable: This active LOW input is used to enable
Input Synchronous Chip Enable: This active LOW input is used to enable
Input Snooze Enable: This active HIGH, asynchronous input causes the
Input Synchronous Chip Enable: This active HIGH input is used to
(continued on next page)
must meet the setup and hold times around the rising edge of
CLK.
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb.
For the x32 and x36 versions, BWa# controls DQa’s and DQPa;
BWb# controls DQb’s and DQPb; BWc# controls DQc’s and DQPc;
BWd# controls DQd’s and DQPd. Parity is only available on the
x18 and x36 versions.
propogate throughout the device. When CKE# is HIGH, the
device ignores the CLK input and effectively internally extends
the previous CLK cycle. This input must meet the setup and hold
times around the rising edge of CLK.
is LOW and is the only means for determining READs and
WRITEs. READ cycles may not be converted into WRITEs (and vice
versa) other than by loading a new address. A LOW on this pin
permits BYTE WRITE operations to meet the setup and hold times
around the rising edge of CLK. Full bus-width WRITEs occur if all
byte write enables are LOW.
write enables and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock’s rising edge.
the device. CE# is sampled only when a new external address is
loaded.
the device and is sampled only when a new external address is
loaded.
device to enter a low-power standby mode in which all data in
the memory array is retained. When ZZ is active, all other inputs
are ignored.
enable the device and is sampled only when a new external
address is loaded.
9
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
PIPELINED ZBT SRAM
©2001, Micron Technology, Inc.