MT55L256L36P MICRON [Micron Technology], MT55L256L36P Datasheet - Page 26

• Manufacturer Part Number: MT55L256L36P
• Description: 8Mb ZBT SRAM
• Manufacturer: MICRON [Micron Technology]

NOP, STALL, AND DESELECT TIMING PARAMETERS
NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a “pause.” A WRITE is not
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
COMMAND
SYM
t
t
KHQX
KHQZ
ADDRESS
ADV/LD#
BWx#
R/W#
CKE#
2. For this waveform, ZZ and OE# are tied LOW.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
CLK
CE#
DQ
MIN
1.5
1.5
performed during this cycle.
recent data may be from the input data register.
-6
MAX
3.5
WRITE
D(A1)
A1
1
MIN
1.5
1.5
-7.5
Q(A2)
READ
A2
2
MAX
3.5
NOP, STALL, AND DESELECT CYCLES
MIN
1.5
1.5
STALL
3
-10
MAX
3.5
D(A1)
Q(A3)
READ
A3
4
UNITS
ns
ns
Q(A2)
26
WRITE
D(A4)
A4
5
8Mb: 512K x 18, 256K x 32/36
STALL
6
Q(A3)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
7
PIPELINED ZBT SRAM
DON’T CARE
D(A4)
Q(A5)
READ
A5
8
DESELECT
9
©2001, Micron Technology, Inc.
t
KHQX
UNDEFINED
CONTINUE
DESELECT
Q(A5)
10
t
KHQZ