MT55L256L36P MICRON [Micron Technology], MT55L256L36P Datasheet - Page 14

• Manufacturer Part Number: MT55L256L36P
• Description: 8Mb ZBT SRAM
• Manufacturer: MICRON [Micron Technology]

BGA PIN DESCRIPTIONS (continued)
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
(a)
1M, 1U, 7A,
6N, 7E, 7G,
(b)
2G, 2K, 2M
1L, 1N, 2E,
7F, 7J, 7M,
1A, 1F, 1J,
2J, 4C, 4J,
4R, 5R, 6J
6F, 6H, 6L,
7K, 7P
x 1 8
1D, 1H,
4 A
6D
7U
4 B
3 R
4 F
2P
–
–
1M, 1U, 7A,
6M, 6N, 7K,
6G, 6H, 7D,
1G, 1H, 2E,
1N, 1P, 2K,
2L, 2M, 2N
7E, 7G, 7H
7F, 7J, 7M,
(a)
(b)
2F, 2G, 2H
(d)
1A, 1F, 1J,
7L, 7N, 7P
2J, 4C, 4J,
4R, 5R, 6J
(c)
x32/x36
6K, 6L,
1K, 1L,
6E, 6F,
1D, 1E,
4 A
6D
2D
7U
4 B
3 R
4 F
6P
2P
S Y M B O L T Y P E
ADV#/LD# Input Synchronous Address Advance/Load: When HIGH, this input is
NF/DQPa
NF/DQPb
NF/DQPd
NF/DQPc
MODE
V
D Q a
D Q b
D Q d
D Q c
OE#
V
N F
DD
DD
Q
Output is DQb’s. For the x32 and x36 versions, Byte “a” is DQa’s;
Supply Power Supply: See DC Electrical Characteristics and Operating
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa’s; Byte “b”
Input Mode: This input selects the burst sequence. A LOW on this
Input Output Enable: This active LOW, asynchronous input enables the
Input No Function: These pins are internally connected to the die and
NF/
I/O
(continued on next page)
data I/O output drivers.
used to advance the internal burst counter, controlling burst
access after the external addressis loaded. When ADV#/LD# is
HIGH, R/W# is ignored. A LOW on ADV#/LD# clocks a new
address at the CLK rising edge.
input selects “linear burst.” NC or HIGH on this input selects
“interleaved burst.” Do not alter input state while device is
operating.
will have the capacitance of input pins. It is allowable to leave
these pins unconnected or driven by signals. These pins are
reserved for address expansion; 4A becomes an SA at 16Mb
density.
Byte “b” is DQb’s; Byte “c” is DQc’s; Byte “d” is DQd’s. Input
data must meet setup and hold times around the rising edge of
CLK.
No Function/Parity Data I/Os: On the x32 version, these are No
Function (NF). On the x18 version, Byte “a” parity is DQPa; Byte
Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity
is DQPd.
Conditions for range.
and Operating Conditions for range.
“b” parity is DQPb. On the x36 version, Byte “a” parity is DQPa;
14
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D E S C R I P T I O N
PIPELINED ZBT SRAM
©2001, Micron Technology, Inc.