XRT83VSH28ES Exar, XRT83VSH28ES Datasheet
XRT83VSH28ES
Specifications of XRT83VSH28ES
Related parts for XRT83VSH28ES
XRT83VSH28ES Summary of contents
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... The LIU programmed through a standard parallel or serial microprocessor interface. EXAR’s LIU has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a power failure or when the LIU is powered off. Key design features within the LIU ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT IGURE LOCK IAGRAM OF THE MCLKE1 MASTER CLOCK SYNTHESIZER channels, CHANNEL _n TPOS_n/ TDATA_n QRSS PATTERN TNEG_n/ CODES _n GENERATOR TCLK_n QRSS DETECTOR RCLK_n RNEG_n/ LCV_n ...
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REV. 2.0.0 FEATURES Fully integrated eight channel short-haul transceivers for E1 (2.048MHz) applications Internal Impedance matching on both receive and transmit for 75 (E1) and 120 (E1) applications are per port selectable through software without changing components ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 4 REV. 2.0.0 ...
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REV. 2.0.0 GENERAL DESCRIPTION................................................................................................. 1 A ............................................................................................................................................... 1 PPLICATIONS XRT83VSH28 E1 LIU (H IGURE LOCK IAGRAM OF THE XRT83VSH28 E1 LIU (H IGURE LOCK IAGRAM OF THE F ..................................................................................................................................................... 3 EATURES ORDERING ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT ABLE ANDOM IT EQUENCE OLYNOMIALS 3.6 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 31 3.7 LINE TERMINATION (TTIP/TRING) ............................................................................................................... IGURE YPICAL ONNECTION IAGRAM ...
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REV. 2.0.0 F 37. MPC86X IGURE ODE IMING T 20 ABLE ICROPROCESSOR EGISTER T 21 ABLE ICROPROCESSOR EGISTER 5.8 CHANNEL CONTROL REGISTERS .............................................................................................................. ABLE ICROPROCESSOR EGISTER T ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT PIN DESCRIPTION BY FUNCTION RECEIVE SECTION BGA IGNAL AME YPE L # EAD RXON K16 I Receiver On Hardware Mode Only This pin is used to enable the receivers for ...
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REV. 2.0.0 BGA IGNAL AME YPE L # EAD RTIP0 C1 I Receive Differential Tip Input RTIP1 G1 RTIP is the positive differential input from the line interface. Along with the RRING signal, these pins should be ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT BGA IGNAL AME YPE L # EAD RXRES1 R10 I Receive External Resistor Control Pins RXRES0 V10 Hardware mode Only These pins are used in the Receive Internal Impedance mode ...
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REV. 2.0.0 TRANSMIT SECTION BGA IGNAL AME YPE L # EAD TCLKE/µPTS2 L15 I Transmit Clock Edge Hardware Mode This pin is used to select which edge of the transmit clock is used to sample data on ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT BGA IGNAL AME YPE L # EAD TCLK0 B4 I Transmit Clock Input TCLK1 A3 TCLK is the input facility clock used to sample the incoming TPOS/TNEG data. If TCLK ...
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REV. 2.0.0 PARALLEL MICROPROCESSOR INTERFACE BGA IGNAL AME EAD YPE # HW/HOST T10 I Mode Control Input This pin is used to select Host mode or Hardware mode. By default, the LIU is set in Hardware ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT BGA IGNAL AME EAD YPE # RDY/EQC4 A6 I/O Ready Output (Data Transfer Acknowledge) Host Mode (Parallel Microprocessor) If Pin SER_PAR is pulled "Low", this output pin from the ...
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REV. 2.0.0 BGA IGNAL AME EAD YPE # µPCLK/ATAOS T13 I Synchronous Microprocessor Clock/Automatic Transmit All Ones Host Mode This synchronous input clock is used as the internal master clock to the microproces- sor interface when ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT CLOCK SYNTHESIZER BGA IGNAL AME YPE L # EAD MCLKOUT H1 O Synthesized Master Clock Output This signal is the output of the Master Clock Synthesizer PLL which is at ...
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REV. 2.0.0 ALARM FUNCTIONS/REDUNDANCY SUPPORT BGA IGNAL AME YPE L # EAD GAUGE J18 I Twisted Pair Cable Wire Gauge Select Hardware Mode Only This pin is used to match the frequency characteristics according to the gauge ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT BGA IGNAL AME YPE L # EAD TERSEL R11 I Termination Impedance Select Hardware Mode Only The TERSEL pin is used to select the transmitter and receiver impedance. By default, ...
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REV. 2.0.0 SERIAL MICROPROCESSOR INTERFACE BGA IGNAL AME YPE L # EAD SER_PAR P18 I SCLK T13 I SDI C10 I SDO R7 O JTAGtip E18 JTAGring B18 TDO B1 TDI R1 TCK N1 TMS E1 SENSE ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT BGA IGNAL AME YPE L # EAD TVDD E4 **** F4 F16 E17 R4 P1 N15 P15 RVDD C2 **** E5 G16 D16 V2 N3 N17 U18 RGND D2 **** ...
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REV. 2.0.0 BGA IGNAL AME YPE L # EAD DGND A1 **** R8 T9 H17 G15 K2 V18 NC A8, B8, I C8, K1, T11 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT D ESCRIPTION Digital ...
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... The LIU features are programmed through a standard microprocessor interface or controlled through Hardware mode. EXAR’s LIU has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a power failure or when the LIU is powered off ...
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REV. 2.0.0 2.0 RECEIVE PATH LINE INTERFACE The receive path of the XRT83VSH28 LIU consists of 8 independent E1 receivers. The following section describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A simplified block diagram of the ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 2.1.2 CASE 2: Internal Termination With One External Fixed Resistor for All Modes Along with the internal termination, a high precision external fixed resistor can be used to optimize the return loss. This ...
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REV. 2.0.0 2.2 Clock and Data Recovery The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the incoming data stream and outputs a clock that’s in phase with the incoming signal. ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 2.2.1 Receive Sensitivity To meet short haul requirements, the XRT83VSH28 can accept E1 signals that have been attenuated by 12dB of flat loss. However, the XRT83VSH28 can tolerate cable loss and flat loss ...
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REV. 2.0.0 2.2.3.1 RLOS (Receiver Loss of Signal) The XRT83VSH28 supports both G.775 or ETSI-300-233 RLOS detection scheme. In G.775 mode, RLOS is declared when the received signal is less than 375mV for 32 consecutive pulse periods (typical). The device ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 2.4 HDB3 Decoder In single rail mode, RPOS can decode AMI or HDB3 signals. HDB3 is defined as any block of 4 successive zeros replaced with 000V or B00V, so that two successive ...
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REV. 2.0.0 2.6 RxMUTE (Receiver LOS with Data Muting) The receive muting function can be selected by setting RxMUTE to "1" in the appropriate global register. If selected, any channel that experiences an RLOS condition will automatically pull RPOS and ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 3.0 TRANSMIT PATH LINE INTERFACE The transmit path of the XRT83VSH28 LIU consists of 8 independent E1 transmitters. The following section describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A ...
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REV. 2.0 ABLE P ARAMETER TCLK Duty Cycle Transmit Data Setup Time Transmit Data Hold Time TCLK Rise Time (10% to 90%) TCLK Fall Time (90 VDD=3.3V ±5%, T =25°C, Unless Otherwise Specified ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 3.3 Transmit Jitter Attenuator The XRT83VSH28 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple timing domains. As the higher data rates are de-multiplexed down to E1 data, ...
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REV. 2.0 IGURE IMPLIFIED LOCK IAGRAM OF THE ATAOS RLOS 3.5.2 QRSS Generation The XRT83VSH28 can transmit a QRSS random sequence to a remote location from TTIP/TRING. The polynomial is shown in Table 8. T ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 3.6 DMO (Digital Monitor Output) The driver monitor circuit is used to detect transmit driver failures by monitoring the activities at TTIP/TRING outputs. Driver failure may be caused by a short circuit in ...
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REV. 2.0.0 4.0 E1 APPLICATIONS This applications section describes common E1 system considerations along with references to application notes available for reference where applicable. 4.1 Loopback Diagnostics The XRT83VSH28 supports several loopback modes for diagnostic testing. The following section describes ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 4.1.3 Digital Loopback With digital loopback activated, the transmit input data at TCLK/TPOS/TNEG is looped back to the receive output data at RCLK/RPOS/RNEG. The digital loopback mode includes the Transmit JA (if enabled). ...
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... System designers can achieve this by implementing common redundancy schemes with the XRT83VSH28 LIU. EXAR offers features that are tailored to redundancy applications while reducing the number of components and providing system designers with solid reference designs. ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 4.2.3 Receive Interface with 1:1 and 1+1 Redundancy The receivers on the backup card should be programmed for "High" impedance. Since there is no external resistor in the circuit, the receivers on the ...
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REV. 2.0.0 4.2.4 N+1 Redundancy Using External Relays N+1 redundancy has one backup card for N primary cards. Due to impedance mismatch and signal contention, external relays are necessary when using this redundancy scheme. The relays create complete isolation between ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 4.2.6 Receive Interface with N+1 Redundancy For N+1 redundancy, the receivers on the primary cards should be programmed for internal impedance. The receivers on the backup card should be programmed for "High" impedance ...
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REV. 2.0.0 4.3 Power Failure Protection For 1:1 or 1+1 line card redundancy in E1 applications, power failure could cause a line card to change the characteristics of the line impedance, causing a degradation in system performance. The XRT83VSH28 was ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 5.0 MICROPROCESSOR INTERFACE The microprocessor interface can be accessed through a standard serial interface (BGA Package Only standard parallel microprocessor interface. The SER_PAR pin is used to select between the two. ...
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REV. 2.0.0 5.1.2 24-Bit Serial Data Input Descritption The serial data input is sampled on the rising edge of SCLK. In readback mode, the serial data output is updated on the falling edge of SCLK. The serial data must be ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT F 30 IGURE IMING IAGRAM FOR THE SCLK SDI ADDR 6 CS SCLK t 29 SDO D0 Hi-Z Don’t Care (Read mode) SDI T ...
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REV. 2.0.0 5.2 Parallel Microprocessor Interface Block The Parallel Microprocessor Interface section supports communication between the local microprocessor (µP) and the LIU. The XRT83VSH28 supports an Intel asynchronous interface, Motorola 68K asynchronous, and an Intel/Motorola interface. The microprocessor interface is ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 5.3 The Microprocessor Interface Block Signals The LIU may be configured into different operating modes and have its performance monitored by software through a standard microprocessor using data, address and control signals. These ...
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REV. 2.0.0 T 13: M ABLE OTOROLA XRT83VSH28 M OTOROLA T YPE AME QUIVALENT IN ALE AS I WR_R/W R/W I RD_DS DS I RDY DTACK O 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT M : ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 5.4 Intel Mode Programmed I/O Access (Asynchronous) If the LIU is interfaced to an Intel type µP, then it should be configured to operate in the Intel mode. Intel type Read and Write ...
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REV. 2.0.0 F 32. I µ IGURE NTEL NTERFACE IGNALS READ OPERATION ALE = ADDR[7:0] Valid Address CS DATA[7: RDY T 14: I ABLE NTEL S P YMBOL ARAMETER t ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 5.5 Motorola Mode Programmed I/O Access (Asynchronous) If the LIU is interfaced to a Motorola type µP, it should be configured to operate in the Motorola mode. Motorola type programmed I/O Read and ...
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REV. 2.0.0 F 33. M 68K µP I IGURE OTOROLA NTERFACE READ OPERATION ADDR[7:0] Valid Address DATA[7: _DS RD _R _DTACK RDY T 15: M ABLE OTOROLA S P ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 5.6 PowerPC 403 Synchronous Mode: In PowerPC mode the active signals are ADDR[7:0], DATA[7:0], CS, R/W (Intel WR), WE (Intel RD), RDY and PCLK. In this mode all input signals are sampled by ...
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REV. 2.0 403 M T IGURE OWER ODE 1 PClk A[17:0] R t27 D[7:0] RDY t24 Note: The value for t25 through t38 can be found in Table 17 Power PC403 Mode Timing ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 5.7 MICROPROCESSOR INTERFACE TIMING - MCP860 SYNCHRONOUS MODE In MPC86x mode the active signals are ADDR[17:0], DATA[7:0], CS, RW, WE, DBEN, TA and PCLK. In this mode all input signals are sampled by ...
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REV. 2.0.0 F 37. MPC86X M T IGURE ODE IMING 1 PClk A[17:0] R t27 D[7:0] RDY t24 Table 19 MPC86X Timing Information - Read Operation Test Conditions 25°C, VCC = 3.3V±5% and 1.8V±5%, unless ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT T 20: M ABLE R EGISTER DDRESS EX N UMBER 0x00 - 0x0F Channel 0 Control Registers 0x10 - 0x1F Channel 1 Control Registers ...
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REV. 2.0.0 T 21: M ABLE R ADDR YPE Global Control Registers for All 8 Channels 128 0x80 R/W SR/DR ATAOS 129 0x81 R/W OVFLO/LCV Reserved 130 0x82 R/W TxONCNTL TERCNTL 131 0x83 R/W Reserved Reserved 140 ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 5.8 Channel Control Registers T 22: M ABLE AME D7 QRSS/ QRSS/PRBS Select Bits PRBS These bits are used to select between QRSS and PRBS QRSS 0 = ...
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REV. 2.0.0 EQC[4: ODE ECEIVE 0x1Ch E1 Short Haul/15dB 0x1Dh E1 Short Haul/15dB T 24: M ABLE AME D7 RxTSEL Receive Termination Select Upon power up, the receiver is in "High" impedance. RxTSEL ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT T 24: M ABLE AME D1 JABW Jitter Bandwidth The jitter bandwidth is a global setting that is applied to both the receiver and transmitter jitter attenuator 10Hz ...
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REV. 2.0.0 T 25: M ABLE AME D3 TxOn Transmit ON/OFF Upon power up, the transmitters are powered off. This bit is used to turn the transmitter for this channel On or Off Transmitter is ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT T 26: M ABLE AME D1 INSBER Insert Bit Error When this bit transitions from a "0" "1", a bit error will be inserted in the transmitted QRSS/PRBS ...
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REV. 2.0 The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the OTE interrupt pin. T 28: M ABLE AME D7 Reserved ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT N : The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the OTE interrupt pin. T 28: M ABLE B ...
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REV. 2.0.0 T 29: M ABLE AME D1 RLOSIS Receiver Loss of Signal Status change 1 = Change in status occurred D0 QRPDIS Quasi Random Pattern Detection Status change 1 = ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 5.9 Global Control Registers T 30: M ABLE R A EGISTER DDRESS AME SR/DR Single-rail/Dual-rail Select: Writing a “1” to this bit configures all ...
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REV. 2.0.0 T 31: M ABLE R A EGISTER DDRESS AME Reserved D6 Reserved D5 Reserved D4 Reserved D3 Reserved D2 RXMUTE Receive Output Mute: Writing a “1” to this bit, ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT T 33: M ABLE AME D7 Reserved This Register Bit is Not Used D6 Reserved This Register Bit is Not Used D5 Reserved This Register Bit is Not Used D4 ...
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REV. 2.0.0 T 34: M ABLE AME D2 BYTEsel LCV Counter Byte Select This bit is used to select the MSB or LSB for Reading the contents of the LCV counter for a given channel. The channel ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT T 36: M ABLE AME D7 Device "ID" The device "ID" of the XRT83VSH28 short haul LIU is 0xF1h. Along with the revision "ID", the device "ID" is used to ...
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REV. 2.0.0 6.0 ELECTRICAL CHARACTERISTICS Storage Temperature Operating Temperature Supply Voltage Vin Maximum Junction Temperature Theta JA Theta ABLE VDD=3.3V ±5 ARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Output High ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT VDD=3.3V ±5 UPPLY M I ODE MPEDANCE V OLTAGE 75 E1 3.3V 120 The typical power consumption of the 1.8V supply represents ~ 36mW of ...
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REV. 2.0 ABLE VDD=3.3V ±5 ARAMETER AMI Output Pulse Amplitude 75 120 Output Pulse Width Output Pulse Width Ratio Output Pulse Amplitude Ratio Jitter Added by the Transmitter Output Output Return Loss ...
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT PACKAGE DIMENSIONS 225 BALL PLASTIC BALL GRID ARRAY (BOTTOM VIEW) D Seating Plane Note: The control dimension is in millimeter. SYMBOL (19.0 X 19.0 ...
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... Changed Device and Revision ID’s EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...