XRT83VSH28ES Exar, XRT83VSH28ES Datasheet - Page 32

• Manufacturer Part Number: XRT83VSH28ES
• Description: Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH (low cost version)
• Manufacturer: Exar

Specifications of XRT83VSH28ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83VSH28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
The XRT83VSH28 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple
timing domains. As the higher data rates are de-multiplexed down to E1 data, stuffing bits are typically
removed which can leave gaps in the incoming data stream. The transmit path has a dedicated jitter attenuator
with a 32-Bit or 64-Bit FIFO that is used to smooth the gapped clock into a steady E1 output. The maximum
gap width of the 8-channel LIU is shown in
N
The XRT83VSH28 has the ability to transmit all ones on a per channel basis by programming the appropriate
channel register. This function takes priority over the digital data present on the TPOS/TNEG inputs. For
example: If a fixed "0011" pattern is present on TPOS in single rail mode and TAOS is enabled, the transmitter
will output all ones. In addition, if digital or dual loopback is selected, the data on the RPOS output will be
equal to the data on the TPOS input.
F
In addition to TAOS, the XRT83VSH28 offers diagnostic features for analyzing network integrity such as
ATAOS and QRSS on a per channel basis by programming the appropriate registers. These diagnostic
features take priority over the digital data present on TPOS/TNEG inputs. The transmitters will send the
diagnostic code to the line and will be maintained in the digital loopback if selected. When the LIU is
responsible for sending diagnostic patterns, the LIU is automatically placed in the single rail mode.
If ATAOS is selected by programming the appropriate global register, an AMI all ones signal will be transmitted
for each channel that experiences an RLOS condition. If RLOS does not occur, the ATAOS will remain inactive
until an RLOS on a given channel occurs. A simplified block diagram of the ATAOS function is shown in
Figure
3.3
3.4
3.5
3.5.1
OTE
IGURE
: If the LIU is used in a loop timing system, the receive path has a dedicated jitter attenuator. See the Receive
Section of this datasheet.
17.
16. TAOS (T
Transmit Jitter Attenuator
TAOS (Transmit All Ones)
Transmit Diagnostic Features
TAOS
ATAOS (Automatic Transmit All Ones)
T
ABLE
RANSMIT
7: M
1
A
AXIMUM
LL
FIFO D
O
1
32-Bit
64-Bit
NES
Figure 16
G
)
EPTH
AP
Table
W
1
IDTH FOR
is a diagram showing the all ones signal at TTIP and TRING.
7.
29
M
ULTIPLEXER
M
AXIMUM
/M
20 UI
50 UI
APPER
G
AP
W
IDTH
A
PPLICATIONS
REV. 2.0.0