XRT83VSH28ES Exar, XRT83VSH28ES Datasheet - Page 63
XRT83VSH28ES
Manufacturer Part Number
XRT83VSH28ES
Description
Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH (low cost version)
Manufacturer
Exar
Datasheet
1.XRT83VSH28ES.pdf
(75 pages)
Specifications of XRT83VSH28ES
Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
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REV. 2.0.0
N
OTE
B
: The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the
D7
D6
D5
D4
D3
D2
IT
interrupt pin.
Reserved
Reserved
LCV/OF
N
DMO
FLS
AIS
AME
T
ABLE
This Register Bit is Not Used.
Digital Monitor Output
The digital monitor output is always active regardless if the inter-
rupt generation is disabled. This bit indicates the DMO activity. An
interrupt will not occur unless the DMOIE is set to "1" in the chan-
nel register 0x04h and GIE is set to "1" in the global register
0xE0h.
0 = No Alarm
1 = Transmit output driver has failures
FIFO Limit Status
The FIFO limit status is always active regardless if the interrupt
generation is disabled. This bit indicates whether the RD/WR
pointers are within 3-Bits. An interrupt will not occur unless the
FLSIE is set to "1" in the channel register 0x04h and GIE is set to
"1" in the global register 0xE0h.
0 = No Alarm
1 = RD/WR FIFO pointers are within ±3-Bits
Line Code Violation / Counter Overflow
This bit serves a dual purpose. By default, this bit monitors the line
code violation activity. However, if bit 7 in register 0x81h is set to a
"1", this bit monitors the overflow status of the internal LCV
counter. An interrupt will not occur unless the LCV/OFIE is set to
"1" in the channel register 0x04h and GIE is set to "1" in the global
register 0x80h.
0 = No Alarm
1 = A line code violation, bipolar violation, or excessive zeros has
occurred
This Register Bit is Not Used.
Alarm Indication Signal
The alarm indication signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the AIS
activity. An interrupt will not occur unless the AISIE is set to "1" in
the channel register 0x04h and GIE is set to "1" in the global regis-
ter 0xE0h.
0 = No Alarm
1 = An all ones signal is detected
28: M
ICROPROCESSOR
C
HANNEL
F
0-7 (0
UNCTION
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
R
60
EGISTER
X
05
H
-0
X
0
75
X
05
H
)
H
B
IT
D
ESCRIPTION
Register
Type
RO
RO
RO
RO
XRT83VSH28
(HW reset)
Default
Value
0
0
0
0
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