XRT83VSH28ES Exar, XRT83VSH28ES Datasheet - Page 54

• Manufacturer Part Number: XRT83VSH28ES
• Description: Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH (low cost version)
• Manufacturer: Exar

Specifications of XRT83VSH28ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83VSH28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
In MPC86x mode the active signals are ADDR[17:0], DATA[7:0], CS, RW, WE, DBEN, TA and PCLK. In this
mode all input signals are sampled by the PCLK. For all inputs minimum setup time is 4ns and minimum hold
time is 3ns. Maximum PCLK frequency is 70 MHz.
A READ cycle starts with RW being 'HIGH' and assertion of CS, address is assumed to be stable at this time
since CS is usually derived from the decoding the address bus.
Following falling edge of CS, DBEN is asserted for the READ operation. DBEN must remain asserted until TA
is asserted by the XRT86SH221 device, which indicates DATA from the addressed location is available on the
data bus. DBEN and CS can be de-asserted when the data has been read by the processor. WE should be high
during the entire read cycle.
Operation with wait-states is also possible, provided the wait is longer than the minimum cycle time. Use of TA
is recommended for timing efficiency since the read cycle time can vary depending on the internal address
location being accessed.
WRITE operation is identical to read operation except that the cycle starts with RW being 'LOW', followed by
CS assertion further followed by assertion of WE. Data to be written at the addressed location should be valid
on the data bus at the time WE is asserted. WE should remain asserted until TA is asserted by the
XRT86SH221 device. Following assertion of TA WE and CS may be de-asserted. DBEN should be high during
the entire write cycle.
F
Table 18
5.7
IGURE
Timing
t23
t24
t25
36. MPC86X M
MICROPROCESSOR INTERFACE TIMING - MCP860 SYNCHRONOUS MODE
MPC86X Mode Timing - Write Operation
R/W "Low" to rising edge of PCLK set-up time (Write
Operation)
CS "Low" to rising edge of PCLK set-up time
Rising edge of PCLK to RDY “High”delay
Test Conditions: TA = 25°C, VCC = 3.3V±5% and 1.8V±5%, unless otherwise specified
A[17:0]
D[7:0]
PClk
RDY
R/W
WE
OE
CS
ODE
T
IMING
1
Description
- W
NOTE: PClk = 33Mhz
After 1 PClk Cycle
2
t24
RITE
t23
O
3
PERATION
4
51
8 PClk Cycles
5
6
7
Min.
5
4
4
8
t25
9
Typ.
-
-
-
10
Max.
-
-
-
REV. 2.0.0
Units
ns
ns
ns