XRT83VSH28ES Exar, XRT83VSH28ES Datasheet - Page 47
XRT83VSH28ES
Manufacturer Part Number
XRT83VSH28ES
Description
Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH (low cost version)
Manufacturer
Exar
Datasheet
1.XRT83VSH28ES.pdf
(75 pages)
Specifications of XRT83VSH28ES
Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
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REV. 2.0.0
XRT83VSH28
P
WR_R/W
RD_DS
IN
RDY
ALE
N
AME
E
QUIVALENT
M
DTACK
OTOROLA
R/W
AS
DS
T
ABLE
P
IN
13: M
T
YPE
O
I
I
I
OTOROLA
Address Strobe: This active high signal is used to latch the contents on the
address bus ADDR[7:0]. The contents of the address bus are latched into the
ADDR[7:0] inputs on the falling edge of TS.
Read/Write: This input pin from the local
whether a Read or Write operation has been requested. When this pin is
pulled “High”, DS will initiate a read operation. When this pin is pulled
“Low”, DS will initiate a write operation.
Data Strobe: This active low input functions as the read or write signal from the
local
is “Low”) the LIU begins the read or write operation.
Data Transfer Acknowledge: This active low signal is provided by the LIU
device. It indicates that the current read or write cycle is complete, and the LIU is
waiting for the next command.
µP dependent on the state of R/W. When DS is pulled “Low” (If CS
M
ODE
: M
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
ICROPROCESSOR
44
D
ESCRIPTION
I
NTERFACE
µP is used to inform the LIU
S
IGNALS
XRT83VSH28
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