XRT83VSH28ES Exar, XRT83VSH28ES Datasheet - Page 6

• Manufacturer Part Number: XRT83VSH28ES
• Description: Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH (low cost version)
• Manufacturer: Exar

Specifications of XRT83VSH28ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83VSH28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
4.0 E1 APPLICATIONS ..............................................................................................................................32
5.0 MICROPROCESSOR INTERFACE ......................................................................................................39
3.6 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 31
3.7 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 31
4.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 32
4.2 LINE CARD REDUNDANCY ........................................................................................................................... 34
4.3 POWER FAILURE PROTECTION .................................................................................................................. 38
4.4 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 38
4.5 NON-INTRUSIVE MONITORING .................................................................................................................... 38
5.1 SERIAL MICROPROCESSOR INTERFACE BLOCK (BGA PACKAGE ONLY) ........................................... 39
5.2 PARALLEL MICROPROCESSOR INTERFACE BLOCK .............................................................................. 42
5.3 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 43
5.4 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) ............................................................... 45
5.5 MOTOROLA MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) .................................................... 47
5.6 POWERPC 403 SYNCHRONOUS MODE: ..................................................................................................... 49
5.7 MICROPROCESSOR INTERFACE TIMING - MCP860 SYNCHRONOUS MODE ........................................ 51
T
F
F
F
F
F
F
F
F
F
F
F
F
F
T
T
F
T
T
T
F
T
F
T
F
T
F
T
F
T
T
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
ABLE
ABLE
IGURE
ABLE
ABLE
ABLE
IGURE
ABLE
IGURE
ABLE
IGURE
ABLE
IGURE
ABLE
IGURE
ABLE
ABLE
4.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 32
4.1.2 REMOTE LOOPBACK ................................................................................................................................................ 32
4.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 33
4.1.4 DUAL LOOPBACK ..................................................................................................................................................... 33
4.2.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 34
4.2.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 34
4.2.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 35
4.2.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 36
4.2.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 36
4.2.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY ................................................................................................... 37
5.1.1 SERIAL TIMING INFORMATION................................................................................................................................ 39
5.1.2 24-BIT SERIAL DATA INPUT DESCRITPTION ......................................................................................................... 40
5.1.3 ADDR[7:0] (SCLK1 - SCLK8) ..................................................................................................................................... 40
5.1.4 R/W (SCLK9)............................................................................................................................................................... 40
5.1.5 DUMMY BITS (SCLK10 - SCLK16) ............................................................................................................................ 40
5.1.6 DATA[7:0] (SCLK17 - SCLK24) ................................................................................................................................. 40
5.1.7 8-BIT SERIAL DATA OUTPUT DESCRIPTION ......................................................................................................... 40
11: XRT83VSH28 M
16 P
17 P
18 MPC86X M
19 MPC86X T
8: R
9: M
10: S
12: I
13: M
14: I
15: M
18. T
19. S
20. S
21. S
22. S
23. S
24. S
25. S
26. S
27. S
28. S
29. T
30. T
31. S
32. I
33. M
34. P
35. P
36. MPC86X M
43
ANDOM
ICROPROCESSOR
NTEL MODE
NTEL
OWER
OWER
ELECTING THE
OTOROLA
NTEL
OTOROLA
YPICAL
IMING
IMING
IMPLIFIED
IMPLIFIED
IMPLIFIED
IMPLIFIED
IMPLIFIED
IMPLIFIED
IMPLIFIED
IMPLIFIED
IMPLIFIED
IMPLIFIED
IMPLIFIED
OWER
OWER
OTOROLA
M
µP I
PC403 M
PC403 M
B
ICROPROCESSOR
D
D
PC 403 M
PC 403 M
IT
C
IAGRAM FOR THE
IAGRAM FOR THE
IMING
ODE
NTERFACE
ONNECTION
: M
S
M
68K M
B
B
B
B
B
B
B
B
B
B
B
68K µP I
ODE
EQUENCE
ODE
LOCK
LOCK
LOCK
LOCK
LOCK
LOCK
LOCK
LOCK
LOCK
LOCK
LOCK
ICROPROCESSOR
M
T
I
ICROPROCESSOR
ODE
ODE
IMING
NFORMATION
: M
T
S
ICROPROCESSOR
ICROPROCESSOR
ODE
ODE
IMING
ERIAL
D
D
D
D
D
D
D
D
D
D
D
ICROPROCESSOR
IAGRAM OF
IAGRAM OF
IAGRAM OF
IAGRAM OF
IAGRAM OF THE
IAGRAM OF THE
IAGRAM OF THE
IAGRAM OF THE
IAGRAM OF A
IAGRAM OF THE
IAGRAM OF THE
T
T
NTERFACE
S
IMING
IMING
P
D
T
T
- W
IGNALS
OLYNOMIALS
IMING
IMING
IAGRAM
- W
I
I
NTERFACE
NTERFACE
RITE
S
M
ERIAL
RITE
ICROPROCESSOR
- W
- R
- R
D
- W
- R
O
I
EAD
S
L
R
D
D
NTERFACE
URING
RITE
U
O
PERATION
EAD
OCAL
I
IGNALS
EAD
EMOTE
IGITAL
UAL
N
SING
NTERFACE
RITE
M
I
PERATION
NTERFACE
I
ON
NTERFACE
T
ICROPROCESSOR
T
O
T
R
T
R
S
M
........................................................................................................................... 30
O
IMING
I
IMINGS
O
RANSMIT
RANSMIT
L
ECEIVE
ECEIVE
ERIAL
O
PERATION
NTERFACE
-I
ICROPROCESSOR
P
O
PERATION
A
I
OOPBACK
PERATION
NTRUSIVE
PERATION
NTERNAL
L
ROGRAMMED
NALOG
PERATION
D
L
OOPBACK
OOPBACK
URING
.................................................................................................................. 51
S
S
M
IGNALS
S
............................................................................................................... 51
( TA = 250C, VDD=3.3V± 5%
PECIFICATIONS
I
I
S
M
ICROPROCESSOR
NTERFACE FOR
NTERFACE FOR
IGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH
T
I
I
ERIAL
NTERFACE FOR
NTERFACE FOR
L
ODE
IMING
.......................................................................................................... 50
......................................................................................................... 49
S
OOPBACK
........................................................................................................ 33
........................................................................................................ 52
T
P
....................................................................................................... 50
M
IGNALS
...................................................................................................... 49
II
ERMINATION
ROGRAMMED
..................................................................................................... 33
.................................................................................................... 32
.................................................................................................... 43
ONITORING
................................................................................................... 42
I
I
I/O R
S
NTERFACE
NTERFACE
PECIFICATIONS
I
NTERFACE
........................................................................................... 44
......................................................................................... 32
EAD AND
........................................................................................ 46
1:1
N+1 R
................................................................................... 31
1:1
N+1 R
A
I
NTERFACE
I/O R
PPLICATION
................................................................................ 39
................................................................................ 41
AND
AND
B
EDUNDANCY
W
LOCK
EDUNDANCY
EAD AND
1+1 R
........................................................................ 48
RITE
1+1 R
.................................................................. 42
................................................................. 39
O
............................................................... 38
AND LOAD
EDUNDANCY
PERATIONS
EDUNDANCY
W
........................................................ 37
RITE
...................................................... 36
O
= 10
PERATIONS
............................................ 46
........................................... 35
......................................... 34
P
F) .................................. 41
I
NTEL AND
............................ 48
M
OTOROLA
REV. 2.0.0
M
ODES