XRT83VSH28ES Exar, XRT83VSH28ES Datasheet - Page 25

• Manufacturer Part Number: XRT83VSH28ES
• Description: Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH (low cost version)
• Manufacturer: Exar

Specifications of XRT83VSH28ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

REV. 2.0.0
The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the
incoming data stream and outputs a clock that’s in phase with the incoming signal. This allows for multi-
channels to arrive from different timing sources and remain independent. In the absence of an incoming
signal, RCLK maintains its timing by using the internal master clock as its reference. The recovered data can
be updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To update data
on the falling edge of RCLK, set RCLKE to "1" in the appropriate global register.
of the receive data updated on the rising edge of RCLK.
updated on the falling edge of RCLK. The timing specifications are shown in
F
F
N
2.2
IGURE
IGURE
OTE
RCLK Rise Time (10% to 90%)
RCLK Fall Time (90% to 10%)
Receive Data Setup Time
Receive Data Hold Time
: VDD=3.3V ±5%, T
RCLK to Data Delay
with 25pF Loading
with 25pF Loading
6. R
7. R
RCLK Duty Cycle
Clock and Data Recovery
P
ARAMETER
ECEIVE
ECEIVE
D
D
ATA
ATA
A
R P O S
R N E G
=25°C, Unless Otherwise Specified
R C L K
o r
U
U
T
RNEG
RCLK
RPOS
PDATED ON THE
PDATED ON THE
ABLE
or
4: T
S
RCLK
RCLK
R
IMING
YMBOL
R
R
R
CDU
HO
SU
DY
R
F
S
R
F
R
ALLING
PECIFICATIONS FOR
ISING
D Y
R
DY
E
DGE OF
E
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
DGE OF
M
150
150
22
45
-
-
-
IN
R
R
RCLK
O H
OH
Figure 7
RCLK
R C L K
RCLK
RCLK/RPOS/RNEG
F
R
T
50
is a timing diagram of the receive data
YP
-
-
-
-
-
RCLK
R C L K
R
F
Table
Figure 6
4.
M
55
40
40
40
AX
-
-
XRT83VSH28
is a timing diagram
U
NITS
ns
ns
ns
ns
ns
%