XRT83VSH28ES Exar, XRT83VSH28ES Datasheet - Page 30

• Manufacturer Part Number: XRT83VSH28ES
• Description: Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH (low cost version)
• Manufacturer: Exar

Specifications of XRT83VSH28ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83VSH28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
The transmit path of the XRT83VSH28 LIU consists of 8 independent E1 transmitters. The following section
describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A simplified
block diagram of the transmit path is shown in
F
In dual rail mode, TPOS and TNEG are the digital inputs for the transmit path. In single rail mode, TNEG has
no function and can be left unconnected. The XRT83VSH28 can be programmed to sample the inputs on
either edge of TCLK. By default, data is sampled on the falling edge of TCLK. To sample data on the rising
edge of TCLK, set TCLKE to "1" in the appropriate global register.
transmit input data sampled on the falling edge of TCLK.
data sampled on the rising edge of TCLK. The timing specifications are shown in
F
F
3.0 TRANSMIT PATH LINE INTERFACE
3.1
IGURE
IGURE
IGURE
TCLK
TPOS
TNEG
13. S
14. T
15. T
TCLK/TPOS/TNEG Digital Inputs
RANSMIT
RANSMIT
IMPLIFIED
HDB3 Encoder
TPOS
TNEG
TCLK
D
D
TPOS
TNEG
TCLK
or
B
or
ATA
ATA
LOCK
S
S
AMPLED ON
AMPLED ON
D
IAGRAM OF THE
Attenuator
Tx Jitter
F
R
ALLING
ISING
Figure
T
E
T
T
RANSMIT
SU
SU
E
DGE OF
Control
Timing
DGE OF
27
13.
P
TCLK
T
T
Figure 15
ATH
TCLK
HO
HO
TCLK
TCLK
Tx Pulse Shaper
& Pattern Gen
F
R
is a timing diagram of the transmit input
Figure 14
TCLK
TCLK
R
F
Line Driver
Table
is a timing diagram of the
5.
TTIP
TRING
REV. 2.0.0