XRT83VSH28ES Exar, XRT83VSH28ES Datasheet - Page 46

• Manufacturer Part Number: XRT83VSH28ES
• Description: Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH (low cost version)
• Manufacturer: Exar

Specifications of XRT83VSH28ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83VSH28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
The LIU may be configured into different operating modes and have its performance monitored by software
through a standard microprocessor using data, address and control signals. These interface signals are
described below in
operate in Intel mode or Motorola mode. When the microprocessor interface is operating in Intel mode, some
of the control signals function in a manner required by the Intel 80xx family of microprocessors. Likewise, when
the microprocessor interface is operating in Motorola mode, then these control signals function in a manner as
required by the Motorola microprocessors.
Figure 33
constant across the two modes.
interface is operating in the Intel mode. Likewise,
microprocessor interface is operating in the Motorola Power PC mode.
5.3
XRT83VSH28
T
ABLE
P
WR_R/W
ADDR[7:0]
µ
DATA[7:0]
RD_DS
P
IN
RDY
PTS[1:0]
IN
ALE
N
CS
N
11: XRT83VSH28 M
AME
The Microprocessor Interface Block Signals
AME
and
E
Table 15
QUIVALENT
T
I
I/O
RDY
YPE
NTEL
ALE
WR
RD
I
I
I
Table 11
T
)
Microprocessor Interface Mode Select Input pins
These three pins are used to specify the microprocessor interface mode. The relationship
between the state of these three input pins, and the corresponding microprocessor mode is
presented in
Bi-Directional Data Bus for register "Read" or "Write" Operations.
Eight-Bit Address Bus Inputs
The XRT83VSH28 LIU microprocessor interface uses a direct address bus. This address bus
is provided to permit the user to select an on-chip register for Read/Write access.
Chip Select Input
This active low signal selects the microprocessor interface of the XRT83VSH28 LIU and
enables Read/Write operations with the on-chip register locations.
P
ABLE
IN
Table 11
ICROPROCESSOR
,
T
12: I
Table 12
YPE
O
Table 12
I
I
I
NTEL MODE
lists and describes those microprocessor interface signals whose role is
Table 10
Address-Latch Enable: This active high signal is used to latch the contents on
the address bus ADDR[7:0]. The contents of the address bus are latched into the
ADDR[7:0] inputs on the falling edge of ALE.
Read Signal: This active low input functions as the read signal from the local
When this pin is pulled “Low” (if CS is “Low”) the LIU is informed that a read oper-
ation has been requested and begins the process of the read cycle.
Write Signal: This active low input functions as the write signal from the local
When this pin is pulled “Low” (if CS is “Low”) the LIU is informed that a write
operation has been requested and begins the process of the write cycle.
Ready Output: This active low signal is provided by the LIU device. It indicates
that the current read or write cycle is complete, and the LIU is waiting for the next
command.
, and
describes the role of some of these signals when the microprocessor
AND
I
NTERFACE
.
: M
Table 13
(For using a Motorola 68K asynchronous
M
ICROPROCESSOR
OTOROLA
Table 13
43
. The microprocessor interface can be configured to
S
IGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH
M
ODES
D
describes the role of these signals when the
ESCRIPTION
I
NTERFACE
D
ESCRIPTION
S
IGNALS
processor, see
REV. 2.0.0
I
NTEL
µ
µ
P.
P.