ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 26

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ADE7878ACPZ

Manufacturer Part Number
ADE7878ACPZ
Description
IC ENERGY METERING 3PH 40LFCSP
Manufacturer
Analog Devices Inc
Datasheets

Specifications of ADE7878ACPZ

Input Impedance
400 KOhm
Measurement Error
0.1%
Voltage - I/o High
2.4V
Voltage - I/o Low
0.4V
Current - Supply
22mA
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
40-WFQFN, CSP Exposed Pad
Meter Type
3 Phase
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LFCSP
No. Of Pins
40
Msl
MSL 1 - Unlimited
Peak Reflow Compatible (260 C)
Yes
Supply Voltage Min
3V
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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ADE7854/ADE7858/ADE7868/ADE7878
THEORY OF OPERATION
ANALOG INPUTS
The ADE7868/ADE7878 have seven analog inputs forming current
and voltage channels. The ADE7854/ADE7858 have six analog
inputs, not offering the neutral current. The current channels
consist of four pairs of fully differential voltage inputs: IAP and
IAN, IBP and IBN, ICP and ICN, and INP and INN. These vol-
tage input pairs have a maximum differential signal of ±0.5 V. In
addition, the maximum signal level on analog inputs for the
IxP/IxN pair is ±0.5 V with respect to AGND. The maximum
common-mode signal allowed on the inputs is ±25 mV. Figure 25
presents a schematic of the input for the current channels and
their relation to the maximum common-mode voltage.
All inputs have a programmable gain amplifier (PGA) with a
possible gain selection of 1, 2, 4, 8, or 16. The gain of IA, IB, and
IC inputs is set in Bits[2:0] (PGA1[2:0]) of the gain register. For
the ADE7868 and ADE7878 only, the gain of the IN input is set
in Bits[5:3] (PGA2[2:0]) of the gain register; thus, a different gain
from the IA, IB, or IC inputs is possible. See Table 44 for details
on the gain register.
The voltage channel has three single-ended voltage inputs: VAP,
VBP, and VCP. These single-ended voltage inputs have a maximum
input voltage of ±0.5 V with respect to VN. In addition, the max-
imum signal level on analog inputs for VxP and VN is ±0.5 V
with respect to AGND. The maximum common-mode signal
allowed on the inputs is ±25 mV. Figure 26 presents a schematic
of the voltage channels inputs and their relation to the maximum
common-mode voltage.
All inputs have a programmable gain with a possible gain
selection of 1, 2, 4, 8, or 16. To set the gain, use Bits[8:6]
(PGA3[2:0]) in the gain register (see Table 44).
Figure 27 shows how the gain selection from the gain register
works in both current and voltage channels.
+500mV
–500mV
Figure 26. Maximum Input Level, Voltage Channels, Gain = 1
V
Figure 25. Maximum Input Level, Current Channels, Gain = 1
CM
V
+500mV
–500mV
1
+ V
V
CM
2
V
1
V
1
DIFFERENTIAL INPUT
+ V
V
V
1
V
COMMON MODE
2
CM
DIFFERENTIAL INPUT
CM
+ V
= 500mV MAX PEAK
V
= ±25mV MAX
COMMON MODE
2
CM
= 500mV MAX PEAK
V
V
= ±25mV MAX
1
CM
V
V
1
2
VAP, VBP,
OR VCP
ICN, OR INN
VN
ICP, OR INP
IAP, IBP,
IAN, IBN,
Rev. D | Page 26 of 96
ANALOG-TO-DIGITAL CONVERSION
The ADE7868/ADE7878 have seven sigma-delta (Σ-Δ) analog-
to-digital converters (ADCs), and the ADE7854/ADE7858 have
six Σ-Δ ADCs. In PSM0 mode, all ADCs are active. In PSM1
mode, only the ADCs that measure the Phase A, Phase B, and
Phase C currents are active. The ADCs that measure the neutral
current and the A, B, and C phase voltages are turned off. In
PSM2 and PSM3 modes, the ADCs are powered down to
minimize power consumption.
For simplicity, the block diagram in Figure 28 shows a first-
order Σ-Δ ADC. The converter is composed of the Σ-Δ modulator
and the digital low-pass filter.
LOW-PASS FILTER
A Σ-Δ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7854/ADE7858/ADE7868/ADE7878, the
sampling clock is equal to 1.024 MHz (CLKIN/16). The 1-bit
DAC in the feedback loop is driven by the serial data stream.
The DAC output is subtracted from the input signal. If the loop
gain is high enough, the average value of the DAC output (and,
therefore, the bit stream) can approach that of the input signal
level. For any given input value in a single sampling interval, the
data from the 1-bit ADC is virtually meaningless. Only when a
large number of samples are averaged is a meaningful result
obtained. This averaging is carried out in the second part of the
ADC, the digital low-pass filter. By averaging a large number of
bits from the modulator, the low-pass filter can produce 24-bit
data-words that are proportional to the input signal level.
The Σ-Δ converter uses two techniques to achieve high resolu-
tion from what is essentially a 1-bit conversion technique. The
first is oversampling. Oversampling means that the signal is
sampled at a rate (frequency) that is many times higher than
the bandwidth of interest. For example, the sampling rate in
the ADE7854/ADE7858/ADE7868/ADE7878 is 1.024 MHz,
ANALOG
R
C
Figure 27. PGA in Current and Voltage Channels
IxP, VyP
NOTES
1. x = A, B, C, N
IxN, VN
+
y = A, B, C.
Figure 28. First-Order
INTEGRATOR
V
IN
V
REF
1-BIT DAC
CLKIN/16
.....10100101.....
K × V
+
GAIN
SELECTION
LATCHED
COMPARATOR
IN
Σ
-∆ ADC
LOW-PASS
DIGITAL
FILTER
24

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