ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 68

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7854/ADE7858/ADE7868/ADE7878
SPI-Compatible Interface
The SPI of the ADE7854/ADE7858/ADE7868/ADE7878 is
always a slave of the communication and consists of four pins
(with dual functions): SCLK/SCL, MOSI/SDA, MISO/HSD, and
SS /HSA. The functions used in the SPI-compatible interface are
SCLK, MOSI, MISO, and SS . The serial clock for a data transfer
is applied at the SCLK logic input. This logic input has a Schmitt
trigger input structure that allows the use of slow rising (and
falling) clock edges. All data transfer operations synchronize
to the serial clock. Data shifts into the ADE78xx at the MOSI
logic input on the falling edge of SCLK and the ADE78xx
samples it on the rising edge of SCLK. Data shifts out of the
ADE7854/ ADE7858/ADE7868/ADE7878 at the MISO logic
output on a falling edge of SCLK and can be sampled by the
master device on the raising edge of SCLK. The most significant
bit of the word is shifted in and out first. The maximum serial
clock frequency supported by this interface is 2.5 MHz. MISO
stays in high impedance when no data is transmitted from the
ADE7854/ADE7858/ADE7868/ADE7878. See
details of the connection between the ADE78xx SPI and a
master device containing an SPI interface.
The SS logic input is the chip select input. This input is used
when multiple devices share the serial bus. Drive the SS input
low for the entire data transfer operation. Bringing SS high
during a data transfer operation aborts the transfer and places
the serial bus in a high impedance state. A new transfer can
then be initiated by returning the SS logic input to low. However,
because aborting a data transfer before completion leaves the
accessed register in a state that cannot be guaranteed, every
time a register is written, its value should be verified by reading
SCLK
MOSI
MISO
SS
0
Figure 83
Figure 84. SPI Read Operation of a 32-Bit Register
0
0
0
0 0 0
for
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1
15 14
REGISTER ADDRESS
it back. The protocol is similar to the protocol used in I
interface.
SPI Read Operation
The read operation using the SPI interface of the ADE7854/
ADE7858/ADE7868/ADE7878 initiate when the master sets the
SS /HSA pin low and begins sending one byte, representing the
address of the ADE7854/ADE7858/ADE7868/ADE7878, on the
MOSI line. The master sets data on the MOSI line starting with
the first high-to-low transition of SCLK. The SPI of the ADE78xx
samples data on the low-to-high transitions of SCLK. The most
significant seven bits of the address byte can have any value, but
as a good programming practice, they should be different from
0111000b, the seven bits used in the I
of the address byte must be 1 for a read operation. Next, the
master sends the 16-bit address of the register that is read. After
the ADE78xx receives the last bit of address of the register on a
low-to-high transition of SCLK, it begins to transmit its contents
on the MISO line when the next SCLK high-to-low transition
occurs; thus, the master can sample the data on a low-to-high
SCLK transition. After the master receives the last bit, it sets the
SS and SCLK lines high and the communication ends. The data
lines, MOSI and MISO, go into a high impedance state. See
Figure 84
1 0
31 30
REGISTER VALUE
Figure 83. Connecting ADE78xx SPI with an SPI Device
for details of the SPI read operation.
ADE78xx
1 0
SCLK/SCL
MOSI/SDA
MISO/HSD
SS/HSA
2
MOSI
MISO
SCK
SS
C protocol. Bit 0 (read/ write )
SPI DEVICE
2
C