ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 56

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7854/ADE7858/ADE7868/ADE7878
In the ADE7854/ADE7858/ADE7868/ADE7878, the phase
apparent powers are accumulated in the AVAHR, BVAHR, and
CVAHR 32-bit signed registers. The apparent energy register
content can roll over to full-scale negative (0x80000000) and
continue increasing in value when the apparent power is posi-
tive. Conversely, if because of offset compensation in the rms
datapath, the apparent power is negative, the energy register
underflows to full-scale positive (0x7FFFFFFF) and continues
to decrease in value.
Bit 4 (VAEHF) in the STATUS0 register is set when Bit 30 of one of
the xVAHR registers changes, signifying one of these registers is
half full. As the apparent power is always positive and the xVAHR
registers are signed, the VA-hour registers become half full when
they increment from 0x3FFFFFFF to 0x4000 0000. Interrupts
attached to Bit VAEHF in the STATUS0 register can be enabled by
setting Bit 4 in the MASK0 register. If enabled, the IRQ0 pin is set
low and the status bit is set to 1 whenever one of the Energy
Registers xVAHR becomes half full. The status bit is cleared and
the IRQ0 pin is set to high by writing to the STATUS0 register
with the corresponding bit set to 1.
Setting Bit 6 (RSTREAD) of the LCYCMODE register enables
a read-with-reset for all xVAHR accumulation registers, that is,
the registers are reset to 0 after a read operation.
Integration Time Under Steady Load
The discrete time sample period for the accumulation register is
125 μs (8 kHz frequency). With full-scale pure sinusoidal signals
on the analog inputs, the average word value representing the
apparent power is PMAX. If the VATHR threshold register is set
at the PMAX level, this means the DSP generates a pulse that
is added at the xVAHR registers every 125 μs.
AVRMS
AIRMS
DETECTION
DETECTION
DETECTION
CROSSING
(PHASE A)
CROSSING
CROSSING
(PHASE B)
(PHASE C)
ZERO-
ZERO-
ZERO-
Figure 69. Line Cycle Apparent Energy Accumulation Mode
LCYCMODE[7:0]
LCYCMODE[7:0]
LCYCMODE[7:0]
ZXSEL[0] IN
ZXSEL[1] IN
ZXSEL[2] IN
AVAGAIN
Rev. D | Page 56 of 96
ACCUMULATOR
VAHR[47:0]
The maximum value that can be stored in the xVAHR
accumulation register before it overflows is 2
0x7FFFFFFF. The integration time is calculated as
Energy Accumulation Mode
The apparent power accumulated in each accumulation register
depends on the configuration of Bits[5:4] (CONSEL[1:0]) in the
ACCMODE register. The various configurations are described
in Table 20.
Table 20. Inputs to VA-Hour Accumulation Registers
CONSEL[1:0]
00
01
10
11
Line Cycle Apparent Energy Accumulation Mode
As described in the Line Cycle Active Energy Accumulation
Mode section, in line cycle energy accumulation mode, the
energy accumulation can be synchronized to the voltage channel
zero crossings allowing apparent energy to be accumulated over an
integral number of half line cycles. In this mode, the ADE7854/
ADE7858/ADE7868/ADE7878 transfer the apparent energy
accumulated in the 32-bit internal accumulation registers into
the xVAHR registers after an integral number of line cycles, as
shown in Figure 69. The number of half line cycles is specified
in the LINECYC register.
Time = 0x7FFF,FFFF × 125 μs = 74 hr 33 min 55 sec
LINECYC[15:0]
CALIBRATION
CONTROL
AVAHR[31:0]
REGISTER
AVAHR
AVRMS × AIRMS
AVRMS × AIRMS
AVRMS × AIRMS
AVRMS × AIRMS
32-BIT
BVAHR
BVRMS × BIRMS
0
BVRMS × BIRMS
VB = −VA − VC
BVRMS × BIRMS
VB = −VA
31
− 1 or
CVAHR
CVRMS × CIRMS
CVRMS × CIRMS
CVRMS × CIRMS
CVRMS × CIRMS
(45)