ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 88

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7854/ADE7858/ADE7868/ADE7878
Bit
Location
12
13
14
15
Table 46. APHCAL, BPHCAL, CPHCAL Registers (Address 0xE614, Address 0xE615, Address 0xE616)
Bit
Location
9:0
15:10
Table 47. PHSIGN Register (Address 0xE617)
Bit
Location
0
1
2
3
4
5
6
7
Bit Mnemonic
CF1LATCH
CF2LATCH
CF3LATCH
Reserved
Bit Mnemonic
PHCALVAL
Reserved
Bit Mnemonic
AWSIGN
BWSIGN
CWSIGN
SUM1SIGN
AVARSIGN
BVARSIGN
CVARSIGN
SUM2SIGN
Default Value
0
0
0
0
Default Value
0000000000
000000
Default Value
0
0
0
0
0
0
0
0
Description
When this bit is set to 1, the content of the corresponding energy registers is latched when a
CF1 pulse is generated. See the Synchronizing Energy Registers with CFx Outputs section.
When this bit is set to 1, the content of the corresponding energy registers is latched when a
CF2 pulse is generated. See the Synchronizing Energy Registers with CFx Outputs section.
When this bit is set to 1, the content of the corresponding energy registers is latched when a
CF3 pulse is generated. See the Synchronizing Energy Registers with CFx Outputs section.
Reserved. This bit does not manage any functionality.
Description
If current channel compensation is necessary, these bits can vary only between 0 and 383.
If voltage channel compensation is necessary, these bits can vary only between 512 and 575.
If the PHCALVAL bits are set with numbers between 384 and 511, the compensation behaves
like PHCALVAL set between 256 and 383.
If the PHCALVAL bits are set with numbers between 512 and 1023, the compensation
behaves like PHCALVAL bits set between 384 and 511.
Reserved. These bits do not manage any functionality.
Description
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase A is positive.
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase A is negative.
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase B is positive.
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase B is negative.
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase C is positive.
1: if the active power identified by Bit 6 (REVAPSEL) bit in the ACCMODE register (total of
fundamental) on Phase C is negative.
0: if the sum of all phase powers in the CF1 datapath is positive.
1: if the sum of all phase powers in the CF1 datapath is negative. Phase powers in the CF1
datapath are identified by Bits[2:0] (TERMSEL1[x]) of the COMPMODE register and by
Bits[2:0] (CF1SEL[x]) of the CFMODE register.
0: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase A is positive. This bit is always 0 for ADE7854.
1: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase A is negative.
0: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase B is positive. This bit is always 0 for ADE7854.
1: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase B is negative.
0: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase C is positive. This bit is always 0 for ADE7854.
1: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase C is negative.
0: if the sum of all phase powers in the CF2 datapath is positive.
1: if the sum of all phase powers in the CF2 datapath is negative. Phase powers in the CF2
datapath are identified by Bits[5:3] (TERMSEL2[x]) of the COMPMODE register and by
Bits[5:3] (CF2SEL[x]) of the CFMODE register.
Rev. D| Page 88 of 96