ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 74

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7854/ADE7858/ADE7868/ADE7878
Table 27. The Read-Only RMS Registers May Show the Wrong Value [er003, Version = 2 Silicon]
Background
Issue
Workaround
Related Issues
Table 28. To Obtain Best Accuracy Performance, Internal Setting Must Be Changed [er004, Version = 2 Silicon]
Background
Issue
Workaround
Related Issues
Table 29. Values Written to the SAGLVL and ZXTOUT Registers May Not Be Immediately Used by ADE7854, ADE7858,
ADE7868, and ADE7878 [er005, Version = 4 Silicon]
Background
Issue
Workaround
Related Issues
SECTION 1. ADE7854/ADE7858/ADE7868/ADE7878 FUNCTIONALITY ISSUES
Reference
Number
er001
er002
er003
er004
er005
This completes the Silicon Anomaly section.
The read-only rms registers (AVRMS, BVRMS, CVRMS, AIRMS, BIRMS, CIRMS, and NIRMS) can be read without restrictions at
any time.
The fixed function DSP of ADE7854, ADE7858, ADE7868, and ADE7878 computes all the powers and rms values in a loop
with a period of 125 μs (8 kHz frequency). If two rms registers are accessed (read) consecutively, the value of the second
register may be corrupted. Consequently, the apparent power computed during that 125 μs cycle is also corrupted. The
rms calculation recovers in the next 125 μs cycle, and all the rms and apparent power values compute correctly.
The issue appears independent of the communication type, SPI or I
consecutive rms readings is lower than 265 μs. The issue affects only the rms registers; all of the other registers of
ADE7854, ADE7858, ADE7868, and ADE7878 can be accessed without any restrictions.
The rms registers can be read one at a time with at least 265 μs between the start of the readings. DREADY interrupt at the
IRQ0 pin can be used to time one rms register reading every three consecutive DREADY interrupts. This ensures 375 μs
between the start of the rms readings.
Alternatively, the rms registers can be read interleaved with readings of other registers that are not affected by this
restriction as long as the time between the start of two consecutive rms register readings is 265 μs.
None.
Internal default settings provide best accuracy performance for ADE7854, ADE7858, ADE7868, and ADE7878.
It was found that if a different setting is used, the accuracy performance can be improved.
To enable a new setting for this internal register, execute two consecutive 8-bit register write operations:
The first write operation: 0xAD is written to Address 0xE7FE.
The second write operation: 0x01 is written to Address 0xE7E2.
The write operations must be executed consecutively without any other read/write operation in between. As a
verification that the value was captured correctly, a simple 8-bit read of Address 0xE7E2 should show the 0x01 value.
None.
Usually, the SAGLVL and ZXTOUT registers initialize immediately after power-up or after a hardware/software reset. After
the run register is set to 1, the phase voltage sag detector (for SAGLVL), and the zero-crossing timeout circuit (for ZXTOUT)
use these values immediately.
After the SAGLVL register is initialized with a new value after power-up or a hardware or software reset, the new value
may be delayed and not available for immediate use by the phase voltage sag detector. However, it is used by the
detector after at least one phase voltage rises above 10% of the full-scale input at the phase voltage ADCs.
After the ZXTOUT register is initialized with a new value after power-up or a hardware or software reset, the new value
may be delayed and not available for immediate use by the zero-crossing timeout circuit. However, the circuit does use
the new value after at least one phase voltage rises above 10% of the full-scale input at the phase voltage ADCs.
Usually, at least one of the phase voltages is greater than 10% of full scale after power-up or after a hardware/software
reset. If this cannot be guaranteed, then the SAGLVL and ZXTOUT registers should be written eight consecutive times to
reduce the probability of not being considered immediately by the phase voltage sag detector and zero-crossing timeout
circuit below 0.2 ppm.
None.
Description
Offset rms registers cannot be set to negative values.
Values written to the CF1DEN, CF2DEN, CF2DEN, SAGLVL, and ZXTOUT registers may not be immediately
used by ADE7854, ADE7858, ADE7868, and ADE7878.
The read-only rms registers may show the wrong value.
To obtain best accuracy performance, internal setting must be changed.
Values written to the SAGLVL and ZXTOUT registers may not be immediately used by ADE7854, ADE7858,
ADE7868, and ADE7878.
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C, when the time between the start of two
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