ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 69

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Write Operation
The write operation using the SPI interface of the ADE78xx
initiates when the master sets the SS /HSA pin low and begins
sending one byte representing the address of the ADE7854/
ADE7858/ADE7868/ADE7878 on the MOSI line. The master
sets data on the MOSI line starting with the first high-to-low
transition of SCLK. The SPI of the ADE78xx samples data on
the low-to-high transitions of SCLK. The most significant seven
bits of the address byte can have any value, but as a good pro-
gramming practice, they should be different from 0111000b, the
SCLK
MOSI
SS
0
0
Figure 85. SPI Write Operation of a 32-Bit Register
0
0
0 0 0 0
Rev. D | Page 69 of 96
15 14
REGISTER ADDRESS
seven bits used in the I
address byte must be 0 for a write operation. Next, the master
sends both the 16-bit address of the register that is written and
the 32-, 16-, or 8-bit value of that register without losing any
SCLK cycle. After the last bit is transmitted, the master sets the
SS and SCLK lines high at the end of the SCLK cycle and the
communication ends. The data lines, MOSI and MISO, go into
a high impedance state. See
operation.
1 0 31 30
ADE7854/ADE7858/ADE7868/ADE7878
REGISTER VALUE
1 0
2
C protocol. Bit 0 (read/ write ) of the
Figure 85
for details of the SPI write