ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 63

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CHECKSUM REGISTER
The ADE7854/ADE7858/ADE7868/ADE7878 have a checksum
32-bit register, CHECKSUM, that ensures certain very important
configuration registers maintain their desired value during
Normal Power Mode PSM0.
The registers covered by this register are MASK0, MASK1,
COMPMODE, gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,
CONFIG, MMODE, ACCMODE, LCYCMODE, HSDC_CFG,
and another six 8-bit reserved internal registers that always have
default values. The ADE78xx computes the cyclic redundancy
check (CRC) based on the IEEE802.3 standard. The registers
are introduced one-by-one into a linear feedback shift register
(LFSR) based generator starting with the least significant bit (as
shown in Figure 77). The 32-bit result is written in the
CHECKSUM register. After power-up or a hardware/software
reset, the CRC is computed on the default values of the registers
giving the results presented in the Table 23.
Table 23. Default Values of CHECKSUM and of Internal
Registers CRC
Part No.
ADE7854
ADE7858
ADE7868
ADE7878
Figure 78 shows how the LFSR works. The MASK0, MASK1,
COMPMODE, gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,
CONFIG, MMODE, ACCMODE, LCYCMODE, and HSDC_CFG
registers, and the six 8-bit reserved internal registers form the
bits [a
bit of the first internal register to enter LFSR; Bit a
significant bit of the MASK0 register, the last register to enter
LFSR. The formulas that govern LFSR are as follows:
255
, a
254
Default Value of
CHECKSUM
0x2689B124
0xD6744F93
0x93D774E6
0x33666787
,…, a
31
255 248
MASK0 MASK1 COMPMODE
0
] used by LFSR. Bit a
0
31
240
0 15
232
LFSR
g
0 15
0
GAIN
0
is the least significant
CRC of Internal
Registers
0x3A7ABC72
0x3E7D0FC1
0x23F7C7B1
0x2D32A389
224
b
Figure 78. LFSR Generator Used in CHECKSUM Register Calculation
0
0
15
CFMODE
g
1
216
255
0
Figure 77. CHECKSUM Register Calculation
is the most
b
1
7
REGISTER
INTERNAL
g
2
Rev. D | Page 63 of 96
40
b
0 7
2
INTERNAL
REGISTER
g
3
b
the CRC. Bit b
significant.
g
polynomial defined by the IEEE802.3 standard as follows:
All of the other g
Equation 51, Equation 52, and Equation 53 must be repeated for
j = 1, 2, …, 256. The value written into the CHECKSUM register
contains the Bit b
after the bits from the reserved internal register have passed
through LFSR, is obtained at Step j = 48 and is presented in the
Table 23.
Two different approaches can be followed in using the CHECK-
SUM register. One is to compute the CRC based on the relations
(47) to (51) and then compare the value against the CHECKSUM
register. Another is to periodically read the CHECKSUM register.
If two consecutive readings differ, it can be assumed that one of
the registers has changed value and therefore, the ADE7854,
ADE7858, ADE7868, or ADE7878 has changed configuration.
The recommended response is to initiate a hardware/software
reset that sets the values of all registers to the default, including
the reserved ones, and then reinitialize the configuration registers.
i
i
32
, i = 0, 1, 2, …, 31 are the coefficients of the generating
(0) = 1, i = 0, 1, 2, …, 31, the initial state of the bits that form
0 7
a
255
ADE7854/ADE7858/ADE7868/ADE7878
G ( x ) = x
x
g
g
FB ( j ) = a
b
b
REGISTER
INTERNAL
,
0
8
5
0
i
(j) = FB ( j ) AND g
a
( j ) = FB ( j ) AND g
+ x
= g
= g
254
,....,
g
1
10
4
31
= g
+ x
= g
24
a
0
32
2
j – 1
,
0
2
2
a
+ x
11
INTERNAL
REGISTER
7
is the least significant bit, and Bit b
= g
1
+ x + 1
b
,
XOR b
i
= g
31
i
a
(256)
coefficients are equal to 0.
26
0
4
= g
+ x
12
= g
16
0
5
,
23
31
i
i = 0, 1, …, 31. The value of the CRC,
= g
0
( j – 1)
XOR b
16
+ x
REGISTER
INTERNAL
7
FB
= g
7
22
= 1
GENERATOR
22
+ x
i − 1
= g
LFSR
0
8
16
( j – 1), i = 1, 2, 3, ..., 31
26
+ x
INTERNAL
REGISTER
7
7
= g
12
31
+ x
= 1
0
0
11
+ x
10
31
+ x
is the most
8
+ x
7
(49)
(50)
(51)
(52)
(53)
+