ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 80

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7854/ADE7858/ADE7868/ADE7878
Address
0xE707
0xEBFF
0xEC00
0xEC01
1
2
3
4
Table 34. HPFDIS Register (Address 0x43B6)
Bit
Location
23:0
Table 35. IPEAK Register (Address 0xE500)
Bit Location
23:0
24
25
26
31:27
Table 36. VPEAK Register (Address 0xE501)
Bit Location
23:0
24
25
26
31:27
Table 37. STATUS0 Register (Address 0xE502)
Bit
Location
0
1
2
3
4
5
R is read, and W is write.
32 ZP = 24- or 20-bit signed or unsigned register that is transmitted as a 32-bit word with 8 or 12 MSBs, respectively, padded with 0s. 32 SE = 24-bit signed register that
is transmitted as a 32-bit word sign extended to 32 bits. 16 ZP = 10-bit unsigned register that is transmitted as a 16-bit word with six MSBs padded with 0s.
U is unsigned register, and S is signed register in twos complement format.
N/A is not applicable.
Bit Mnemonic
AEHF
FAEHF
REHF
FREHF
VAEHF
LENERGY
Register
Name
Version
Reserved
LPOILVL
CONFIG2
Default
Value
00000000
Bit Mnemonic
VPEAKVAL[23:0]
VPPHASE[0]
VPPHASE[1]
VPPHASE[2]
Bit Mnemonic
IPEAKVAL[23:0]
IPPHASE[0]
IPPHASE[1]
IPPHASE[2]
R/W
R/W
R/W
R/W
Description
When HPFDIS = 0x00000000, then all high-pass filters in voltage and current channels are enabled. When the
register is set to any nonzero value, all high-pass filters are disabled.
Default Value
0
0
0
0
0
0
1
Default Value
0
0
0
0
00000
Default Value
0
0
0
0
00000
8
8
Bit
Length
8
8
Description
When this bit is set to 1, it indicates that Bit 30 of any one of the total active energy
registers (AWATTHR, BWATTHR, or CWATTHR) has changed.
When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental active
energy registers, FWATTHR, BFWATTHR, or CFWATTHR, has changed. This bit is always 0
for ADE7854, ADE7858, and ADE7868.
When this bit is set to 1, it indicates that Bit 30 of any one of the total reactive energy
registers (AVARHR, BVARHR, or CVARHR) has changed. This bit is always 0 for ADE7854.
When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental reactive
energy registers, AFVARHR, BFVARHR, or CFVARHR, has changed. This bit is always 0 for
ADE7854, ADE7858, and ADE7868.
When this bit is set to 1, it indicates that Bit 30 of any one of the apparent energy
registers (AVAHR, BVAHR, or CVAHR) has changed.
When this bit is set to 1, in line energy accumulation mode, it indicates the end of an
integration over an integer number of half line cycles set in the LINECYC register.
Bit Length
During
Communication
8
8
8
8
Description
These bits contain the peak value determined in the current channel.
When this bit is set to 1, Phase A current generated IPEAKVAL[23:0] value.
When this bit is set to 1, Phase B current generated IPEAKVAL[23:0] value.
When this bit is set to 1, Phase C current generated IPEAKVAL[23:0] value.
These bits are always 0.
Description
These bits contain the peak value determined in the voltage channel.
When this bit is set to 1, Phase A voltage generated VPEAKVAL[23:0] value.
When this bit is set to 1, Phase B voltage generated VPEAKVAL[23:0] value.
When this bit is set to 1, Phase C voltage generated VPEAKVAL[23:0] value.
These bits are always 0.
Rev. D | Page 80 of 96
2
Type
U
U
U
3
Default
Value
0x07
0x00
4
Description
Version of die.
This address can be used in manipulating
the SS/HSA pin when SPI is chosen as
the active port. See the
section for details.
Overcurrent threshold used during
PSM2 mode (ADE7868 and ADE7878
only). See Table 54 in which the register
is detailed.
Configuration register used during
PSM1 mode. See Table 55.
Serial Interfaces