ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 55

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Apparent Power Gain Calibration
The average apparent power result in each phase can be scaled
by ±100% by writing to one of the phase’s VAGAIN 24-bit registers
(AVAGAIN, BVAGAIN, or CVAG AIN). The VAGAIN registers
are twos complement, signed registers and have a resolution of
2
mathematically as
The output is scaled by –50% by writing 0xC00000 to the
xVAGAIN registers, and it is increased by +50% by writing
0x400000 to them. These registers calibrate the apparent power
(or energy) calculation in the ADE7854/ADE7858/ADE7868/
ADE7878 for each phase.
As previously stated in the Current Waveform Gain Registers
section, the serial ports of the ADE78xx work on 32-, 16-, or 8-bit
words and the DSP works on 28 bits. Similar to registers presented
in Figure 33, the AVAGAIN, BVAGAIN, and CVAGAIN 24-bit
registers are accessed as 32-bit registers with the four MSBs
padded with 0s and sign extended to 28 bits.
Apparent Power Offset Calibration
Each rms measurement includes an offset compensation register
to calibrate and eliminate the dc component in the rms value
(see the Root Mean Square Measurement section). The voltage
and current rms values are multiplied together in the apparent
power signal processing. As no additional offsets are created in
the multiplication of the rms values, there is no specific offset
compensation in the apparent power signal processing. The offset
compensation of the apparent power measurement in each phase is
accomplished by calibrating each individual rms measurement.
Apparent Power Calculation Using VNOM
The ADE7854/ADE7858/ADE7868/ADE7878 can compute the
apparent power by multiplying the phase rms current by an rms
voltage introduced externally in the VNOM 24-bit signed register.
When one of Bits[13:11] (VNOMCEN, VNOMBEN, or
VNOMAEN) in the COMPMODE register is set to 1, the
apparent power in the corresponding phase (Phase x for
VNOMxEN) is computed in this way. When the VNOMxEN
bits are cleared to 0, the default value, then the arithmetic
apparent power is computed.
The VNOM register contains a number determined by U, the
desired rms voltage, and
tage when the ADC inputs are at full scale:
where U is the nominal phase rms voltage.
−23
/LSB. The function of the xVAGAIN registers is expressed
V
VNOM
Average
rms
×
I
=
Apparent
rms
U
U
FS
×
×
⎛
⎜
⎝
, 4
1
191
Power
+
U
,
VAGAIN
910
FS
, the rms value of the phase vol-
=
2
23
Register
⎞
⎟
⎠
(41)
(42)
Rev. D | Page 55 of 96
As stated in the Current Waveform Gain Registers, the serial
ports of the ADE78xx work on 32-, 16-, or 8-bit words. Similar
to the register presented in Figure 34, the VNOM 24-bit signed
register is accessed as a 32-bit register with the eight MSBs
padded with 0s.
Apparent Energy Calculation
Apparent energy is defined as the integral of apparent power.
Similar to active and reactive powers, the ADE7854/ADE7858/
ADE7868/ADE7878 achieve the integration of the apparent power
signal in two stages (see Figure 68). The first stage is conducted
inside the DSP: every 125 μs (8 kHz frequency), the instanta-
neous phase apparent power is accumulated into an internal
register. When a threshold is reached, a pulse is generated at the
processor port and the threshold is subtracted from the internal
register. The second stage is conducted outside the DSP and
consists of accumulating the pulses generated by the processor
into internal 32-bit accumulation registers. The content of these
registers is transferred to the VA-hour registers, xVAHR, when
these registers are accessed. Figure 63 from the Active Energy
Calculation section illustrates this process. The VATHR 48-bit
register contains the threshold. Its value depends on how much
energy is assigned to one LSB of the VA-hour registers. When a
derivative of apparent energy (VAh) of [10
integer, is desired as one LSB of the xVAHR register; then, the
xVATHR register can be computed using the following equation:
where:
PMAX = 33,516,139 = 0x1FF6A6B, the instantaneous power
computed when the ADC inputs are at full scale.
f
instantaneous power.
U
the ADC inputs are at full scale.
VATHR is a 48-bit register. As previously stated in the Current
Waveform Gain Registers section, the serial ports of the ADE7854/
ADE7858/ADE7868/ADE7878 work on 32-, 16-, or 8-bit words.
Similar to the WTHR register presented in Figure 64, the VATHR
register is accessed as two 32-bit registers (VATHR1 and VATHR0),
each having eight MSBs padded with 0s.
This discrete time accumulation or summation is equivalent to
integration in continuous time following the description in
Equation 44.
where:
n is the discrete time sample number.
T is the sample period.
S
FS
= 8 kHz, the frequency with which the DSP computes the
, I
ADE7854/ADE7858/ADE7868/ADE7878
Apparent Energy = ∫ s ( t ) dt
VATHR
FS
ApparentEn
are the rms values of phase voltages and currents when
=
PMAX
ergy
=
U
×
∫
FS
f
s
s
( )
×
×
t
3600
I
dt
FS
=
×
Lim
T
10
→
0
n
⎧
⎨
⎩
n
∑
∞
=
0
n
s
VAh], where n is an
( )
nT
×
T
⎫
⎬
⎭
(43)
(44)