Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 157

ADAPTER ICE Z8 ENCORE 64K 64LQFP

Z8F64220100ZDA

Manufacturer Part Number
Z8F64220100ZDA
Description
ADAPTER ICE Z8 ENCORE 64K 64LQFP
Manufacturer
Zilog
Datasheets

Specifications of Z8F64220100ZDA

Module/board Type
*
For Use With/related Products
Z8 Encore!™
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3403
PS019921-0308
Start and Stop Conditions
Master Write and Read Transactions
The master (I
transaction, the I
Low while SCL is High. To complete a transaction, the I
condition by creating a low-to-high transition of the SDA signal while the SCL signal is
high. The START and STOP bits in the I
Start and Stop conditions. A master is also allowed to end one transaction and begin a new
one by issuing a Restart. This is accomplished by setting the START bit at the end of a
transaction, rather than the STOP bit. Note that the Start condition not sent until the
START bit is set and data has been written to the I
The following sections provide a recommended procedure for performing I
read transactions from the I
software should rely on the TDRE, RDRF and NCKI bits of the status register (these bits
generate interrupts) to initiate software actions. When using interrupts or DMA, the TXI
bit is set to start each transaction and cleared at the end of each transaction to eliminate a
‘trailing’ Transmit interrupt.
Caution should be used in using the ACK status bit within a transaction because it is
difficult for software to tell when it is updated by hardware.
When writing data to a slave, the I
the data register has not been written with the next value to be sent (TDRE bit in the I
Status register = 1). In this scenario where software is not keeping up with the I
(TDRE asserted longer than one byte time), the Acknowledge clock cycle for byte n is
delayed until the Data register is written with byte n + 1, and appears to be grouped with
the data clock cycles for byte n+1. If either the START or STOP bit is set, the I
pause prior to the Acknowledge cycle because no additional data is sent.
When a Not Acknowledge condition is received during a write (either during the address
or data phases), the I
and pause until either the STOP or START bit is set. Unless the Not Acknowledge was
received on the last byte, the Data register will already have been written with the next
address or data byte to send. In this case the FLUSH bit of the Control register should be
set at the same time the STOP or START bit is set to remove the stale transmit data and
enable subsequent Transmit interrupts.
When reading data from the slave, the I
the receive interrupt is serviced and the RDRF bit of the status register is cleared by
In order for a receive (read) DMA transaction to send a Not Acknowledge
on the last byte, the receive DMA must be set up to receive n-1 bytes, then
software must set the NAK bit and receive the last (nth) byte directly.
2
C) drives all Start and Stop signals and initiates all transactions. To start a
2
C Controller generates a START condition by pulling the SDA signal
2
C Controller generates the Not Acknowledge interrupt (NCKI = 1)
2
C Controller (master) to slave I
2
C pauses at the beginning of the Acknowledge cycle if
2
C pauses after the data Acknowledge cycle until
2
C Control register control the sending of the
2
C Data register.
Z8 Encore! XP
2
C Controller generates a Stop
2
C devices. In general
Product Specification
®
F64XX Series
2
C write and
I2C Controller
2
C does not
2
C bus
2
C
143

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