Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 81
![ADAPTER ICE Z8 ENCORE 64K 64LQFP](/photos/9/2/90272/z8f64220100zda_sml.jpg)
Z8F64220100ZDA
Manufacturer Part Number
Z8F64220100ZDA
Description
ADAPTER ICE Z8 ENCORE 64K 64LQFP
Manufacturer
Zilog
Specifications of Z8F64220100ZDA
Module/board Type
*
For Use With/related Products
Z8 Encore!™
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3403
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Table 24. Interrupt Request 0 Register (IRQ0)
Interrupt Control Register Definitions
BITS
FIELD
RESET
R/W
ADDR
PS019921-0308
Interrupt Request 0 Register
T2I
7
For all interrupts other than the Watchdog Timer interrupt, the interrupt control registers
enable individual interrupts, set interrupt priorities, and indicate interrupt requests.
The Interrupt Request 0 (IRQ0) register
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the interrupt controller passes an interrupt request to the eZ8
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 0 register to determine if any interrupt requests are pending
T2I—Timer 2 Interrupt Request
0 = No interrupt request is pending for Timer 2.
1 = An interrupt request from Timer 2 is awaiting service.
that are received between execution of the first LDX command and the last
LDX command are lost.
Interrupt Request registers is recommended:
To avoid missing interrupts, the following style of coding to set bits in the
T1I
6
Poor coding style that can result in lost interrupt requests:
Good coding style that avoids lost interrupt requests:
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
ORX IRQ0, MASK
T0I
5
U0RXI
4
FC0H
R/W
(Table
0
U0TXI
24) stores the interrupt requests for both
3
Z8 Encore! XP
I2CI
2
Product Specification
SPII
®
1
Interrupt Controller
F64XX Series
™
CPU. If
ADCI
0
67
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