CRD4525-Q1 Cirrus Logic Inc, CRD4525-Q1 Datasheet - Page 33

• Manufacturer Part Number: CRD4525-Q1
• Description: REFERENCE BOARD FOR CS4525 PWM
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r

Specifications of CRD4525-Q1

• Amplifier Type: Class D
• Output Type: 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 15W x 2 @ 8 Ohm
• Voltage - Supply: 12 V ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Board Type: Fully Populated
• Utilized Ic / Part: CS4525
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1586

DS726PP3
6.1.4.6
The CS4525 implements 5 fully programmable parametric EQ filters.
The filters are implemented in the bi-quad form shown below.
This architecture is represented by the equation shown below where y[n] represents the output sample
value and x[n] represents the input sample value.
The coefficients are represented in binary form by 24-bit signed values stored in 3.21 two’s complement
format. The 3 MSB’s represent the sign bit and the whole-number portion of the decimal coefficient, and
the 21 LSB’s represent the fractional portion of the decimal coefficient. The coefficient values must be in
the range of -4.00000 decimal (80 00 00 hex) to 3.99996 decimal (7F FF FF hex).
The binary coefficient values are stored in registers 0Ah - 54h. Each 24-bit coefficient is split into 3 bytes,
each of which is mapped to an individually accessible register location. See the
ence” section beginning on page 66
By default, all b
plements a pass-through function.
The parametric equalizers be independently enabled and disabled for channels A and B with the En-
ChAPEq and EnChBPEq bits located in the EQ Config register.
Referenced Control
EnChAPEq ..........................
EnChBPEq ..........................
x[n]
Parametric EQ
0
coefficients are set to 1 decimal, and all other coefficients are set to 0 decimal. This im-
Register Location
“Enable Channel A Parametric EQ (EnChAPEq)” on page 79
“Enable Channel B Parametric EQ (EnChBPEq)” on page 79
y[n] = b
Z
Z
-1
-1
0
Figure 16. Bi-Quad Filter Architecture
x[n] + b
Equation 1. Bi-Quad Filter Equation
b
b
b
0
1
2
for the specific register locations for each coefficient.
1
x[n-1] + b
2
x[n-2] + a
1
y[n-1] + a
a
a
1
2
2
y[n-2]
Z
Z
-1
-1
“Register Quick Refer-
y[n]
CS4525
33