STEVAL-IFS012V1 STMicroelectronics, STEVAL-IFS012V1 Datasheet - Page 102
STEVAL-IFS012V1
Manufacturer Part Number
STEVAL-IFS012V1
Description
BOARD ST72651AR6/STTS75/STLM20
Manufacturer
STMicroelectronics
Specifications of STEVAL-IFS012V1
Sensor Type
Temperature
Sensing Range
Depends on IC
Interface
I²C, USB
Sensitivity
Depends on IC
Voltage - Supply
5V
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
ST72F651AR6, STTS75, STLM20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8419
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ST72651AR6
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.6.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Reset Value: 0000 xxxx (0xh)
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider Enable.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to
mode SCK
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
102/161
SPIE SPE
SPIF=1, MODF=1 or OVR=1 in the SPICSR
register
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
7
Section
Section
Frequency.
SPR2
11.6.5.1
11.6.5.1
MSTR
CPOL
Master
Master
Table 32 SPI Master
CPHA
Mode
Mode
SPR1
Doc ID 7215 Rev 4
SPR0
Fault
Fault
0
Bit 3 = CPOL Clock Polarity.
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 2 = CPHA Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
1: The second clock transition is the first capture
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency.
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
Note: These 2 bits have no effect in slave mode.
Table 32. SPI Master mode SCK Frequency
edge.
edge.
Serial Clock
f
f
f
f
f
f
CPU
CPU
CPU
CPU
CPU
CPU
/16
/32
/64
/2
/4
/8
SPR2
1
0
0
1
0
0
SPR1
0
0
0
1
1
1
SPR0
0
0
1
0
0
1
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