STEVAL-IFS012V1 STMicroelectronics, STEVAL-IFS012V1 Datasheet - Page 105

• Manufacturer Part Number: STEVAL-IFS012V1
• Description: BOARD ST72651AR6/STTS75/STLM20
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFS012V1

• Sensor Type: Temperature
• Sensing Range: Depends on IC
• Interface: I²C, USB
• Sensitivity: Depends on IC
• Voltage - Supply: 5V
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST72F651AR6, STTS75, STLM20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8419

11.7 I²C SINGLE MASTER BUS INTERFACE (I2C)
11.7.1 Introduction
The I
tween the microcontroller and the serial I
provides single master functions, and controls all
I
It supports fast I²C mode (400kHz).
11.7.2 Main Features
■
11.7.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the I
bus by a data pin (SDAI) and by a clock pin (SCLI).
It can be connected both with a standard I
Figure 62. I
2
C bus-specific sequencing, protocol and timing.
– Parallel bus /I
– Interrupt generation
– Standard I
– 7-bit Addressing
– End of byte transmission flag
– Transmitter/Receiver flag
– Clock generation
I
2
C single Master Mode
2
C Bus Interface serves as an interface be-
2
SCL
SDA
C BUS Protocol
2
C mode/Fast I
CONDITION
2
C protocol converter
START
2
C mode
MSB
1
2
C bus. It
2
2
Doc ID 7215 Rev 4
C bus
2
C
and a Fast I
ware.
Mode Selection
The interface can operate in the two following mo-
des:
– Master transmitter/receiver
By default, it is idle.
The interface automatically switches from idle to
master after it generates a START condition and
from master to idle after it generates a STOP
condition.
Communication Flow
The interface initiates a data transfer and genera-
tes the clock signal. A serial data transfer always
begins with a start condition and ends with a stop
condition. Both start and stop conditions are gene-
rated by software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte following the start condi-
tion is the address byte.
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to
ure
62.
8
2
C bus. This selection is made by soft-
ACK
9
CONDITION
STOP
ST72651AR6
VR02119B
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Fig-