STEVAL-IFS012V1 STMicroelectronics, STEVAL-IFS012V1 Datasheet - Page 81

BOARD ST72651AR6/STTS75/STLM20

STEVAL-IFS012V1

Manufacturer Part Number
STEVAL-IFS012V1
Description
BOARD ST72651AR6/STTS75/STLM20
Manufacturer
STMicroelectronics
Datasheets

Specifications of STEVAL-IFS012V1

Sensor Type
Temperature
Sensing Range
Depends on IC
Interface
I²C, USB
Sensitivity
Depends on IC
Voltage - Supply
5V
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
ST72F651AR6, STTS75, STLM20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8419

Available stocks

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Price
Part Number:
STEVAL-IFS012V10
Manufacturer:
ST
0
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
2. If the OCiE bit is not set, the OCMPi pin is a
3. When the timer clock is f
4. The output compare functions can be used both
5. The value in the 16-bit OC
Figure 45. Output Compare Block Diagram
16-bit
ister, the output compare function is inhibited
until the OCiLR register is also written.
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
OCMPi are set while the counter value equals
the OCiR register value (see
page
When the timer clock is f
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new timeout period.
16 BIT FREE RUNNING
OC1R Register
OUTPUT COMPARE
16-bit
82).
CIRCUIT
OC2R Register
COUNTER
16-bit
Figure on page
CPU
i
R register and the
CPU
/4, f
/2, OCFi and
OC1E
Figure 46 on
CPU
OCIE
82).
OC2E
OCF1
/8 or in
Doc ID 7215 Rev 4
FOLV2 FOLV1
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
(Control Register 2) CR2
(Control Register 1) CR1
OCF2
CC1
(Status Register) SR
OLVL2
CC0
0
0
OLVL1
0
Latch
Latch
1
2
ST72651AR6
OCMP1
OCMP2
Pin
Pin
81/161
1

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