STEVAL-IFS012V1 STMicroelectronics, STEVAL-IFS012V1 Datasheet - Page 85

• Manufacturer Part Number: STEVAL-IFS012V1
• Description: BOARD ST72651AR6/STTS75/STLM20
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFS012V1

• Sensor Type: Temperature
• Sensing Range: Depends on IC
• Interface: I²C, USB
• Sensitivity: Depends on IC
• Voltage - Supply: 5V
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST72F651AR6, STTS75, STLM20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8419

16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (TCR2)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode). Whatever the value of the OC1E bit,
the internal Output Compare 1 function of the timer
remains active.
0: OCMP1 pin alternate function disabled (I/O pin
1: OCMP1 pin alternate function enabled.
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the internal Output Compare 2 function of the timer
remains active.
0: OCMP2 pin alternate function disabled (I/O pin
1: OCMP2 pin alternate function enabled.
Bits 5:4 = Reserved, forced by hardware to 0.
Bits 3:2 = CC[1:0] Clock Control.
The timer clock mode depends on these bits:
Table 27. Clock Control Bits
Bits 1:0 = Reserved, forced by hardware to 0.
OC1E OC2E
free for general-purpose I/O).
free for general-purpose I/O).
7
Timer Clock
Reserved
f
f
f
CPU
CPU
CPU
/ 4
/ 2
/ 8
0
0
CC1 CC0
CC1
0
0
1
1
0
CC0
0
1
0
1
Doc ID 7215 Rev 4
0
0
STATUS REGISTER (TSR)
Read Only
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
Bit 7 = Reserved, forced by hardware to 0.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh
Note: Reading or writing the ACLR register does
not clear TOF.
Bit 4 = Reserved, forced by hardware to 0.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
Bits 2:0 = Reserved, forced by hardware to 0.
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
7
0
OCF1
TOF
0
OCF2
ST72651AR6
0
0
85/161
0
0