MC56F8367EVME Freescale Semiconductor, MC56F8367EVME Datasheet - Page 121

• Manufacturer Part Number: MC56F8367EVME
• Description: EVAL BOARD FOR MC56F83X
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of MC56F8367EVME

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC56F8145-67 and MC56F8345-67
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F83xx
• Rohs Compliant: Yes
• For Use With/related Products: MC56F83x5, MC56F83x6, MC56F83x7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Two Input/Output pins associated with GPIOD can function as GPIO, EMI (default peripheral) or CAN2
(NOT available on the 56F8167 device) signals. GPIO is the default and is enabled/disabled via the
GPIOD_PER, as shown in
peripheral input/output, then the choice between EMI and CAN2 inputs/outputs is made here in the GPS.
Freescale Semiconductor
Preliminary
1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control bits is
2. Reset configuration
3. Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins.
GPIO Input
GPIO Output
Quad Timer Input / Quad
Decoder Input
Quad Timer Output / Quad
Decoder Input
SPI input
SPI output
used for each pin.
Pin Function
Figure 6-10 Overall Control of GPIOC Pads Using SIM_GPS Control
2
3
Table 6-2 Control of GPIOC Pads Using SIM_GPS Control
Quad Timer Controlled
0
0
1
1
1
1
Figure 6-11
SPI Controlled
—
—
—
—
0
1
SIM_ GPS Register
Control Registers
56F8367 Technical Data, Rev. 8
and
GPIO Controlled
Table
—
—
0
0
1
1
0
1
GPIOC_PER Register
6-3. When GPIOD[1:0] are programmed to operate as
—
—
—
—
0
1
0
1
See the “Switch Matrix for Inputs to the Timer”
table in the 56F8300 Peripheral User Manual
for the definition of timer inputs based on the
Quad Decoder mode configuration.
See SPI controls for determining the direction
of each of the SPI pins.
I/O Pad Control
Comments
1
Register Descriptions
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