MC56F8367EVME Freescale Semiconductor, MC56F8367EVME Datasheet - Page 49

• Manufacturer Part Number: MC56F8367EVME
• Description: EVAL BOARD FOR MC56F83X
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of MC56F8367EVME

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC56F8145-67 and MC56F8345-67
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F83xx
• Rohs Compliant: Yes
• For Use With/related Products: MC56F83x5, MC56F83x6, MC56F83x7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.6 EOnCE Memory Map
4.7 Peripheral Memory Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read/written using word accesses only.
Freescale Semiconductor
Preliminary
:X:$FF FFA0
X:$FF FFFC
X:$FF FFFD
X:$FF FF8A
X:$FF FF8E
X:$FF FF9A
X:$FF FF9B
X:$FF FF9C
X:$FF FF9D
X:$FF FF9E
X:$FF FFFE
X:$FF FFFF
X:$FF FF90
X:$FF FF91
X:$FF FF92
X:$FF FF93
X:$FF FF94
X:$FF FF95
X:$FF FF96
X:$FF FF97
X:$FF FF98
X:$FF FF99
X:$FF FF9F
Address
OCR (bits)
OESCR
OBCNTR
OBMSK (32 bits)
—
OBAR2 (32 bits)
—
OBAR1 (24 bits)
—
OBCR (24 bits)
—
OTB (21-24 bits/stage)
—
OTBPR (8 bits)
OTBCR
OBASE (8 bits)
OSR
OSCNTR (24 bits)
—
OCLSR (8 bits)
OTXRXSR (8 bits)
OTX / ORX (32 bits)
OTX1 / ORX1
Register Acronym
Table 4-8 EOnCE Memory Map
56F8367 Technical Data, Rev. 8
Reserved
External Signal Control Register
Reserved
Breakpoint Unit [0] Counter
Reserved
Breakpoint 1 Unit [0] Mask Register
Breakpoint 1 Unit [0] Mask Register
Breakpoint 2 Unit [0] Address Register
Breakpoint 2 Unit [0] Address Register
Breakpoint 1 Unit [0] Address Register
Breakpoint 1 Unit [0] Address Register
Breakpoint Unit [0] Control Register
Breakpoint Unit [0] Control Register
Trace Buffer Register Stages
Trace Buffer Register Stages
Trace Buffer Pointer Register
Trace Buffer Control Register
Peripheral Base Address Register
Status Register
Instruction Step Counter
Instruction Step Counter
Control Register
Reserved
Core Lock / Unlock Status Register
Transmit and Receive Status and Control Register
Transmit Register / Receive Register
Transmit Register Upper Word
Receive Register Upper Word
Register Name
EOnCE Memory Map
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