EVAL-ADUC7032QSPZ Analog Devices Inc, EVAL-ADUC7032QSPZ Datasheet - Page 101
![EVAL DEV QUICK START ADUC7032](/photos/9/24/92482/eval-aduc7032qspz_sml.jpg)
EVAL-ADUC7032QSPZ
Manufacturer Part Number
EVAL-ADUC7032QSPZ
Description
EVAL DEV QUICK START ADUC7032
Manufacturer
Analog Devices Inc
Series
QuickStart™ PLUS Kitr
Type
MCUr
Datasheet
1.EVAL-ADUC7032QSPZ.pdf
(116 pages)
Specifications of EVAL-ADUC7032QSPZ
Contents
Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
For Use With/related Products
ADuC7032
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 101 of 116
- Download datasheet (3Mb)
SPI Status Register
Name: SPISTA
Address: 0xFFFF0A00
Default Value: 0x00
Access: Read only
Function: This 8-bit MMR represents the current status of the serial peripheral interface.
Table 90. SPISTA MMR Bit Designations
Bit
7 to 6
5
4
3
2
1
0
SPI Divider Register
Name: SPIDIV
Address: 0xFFFF0A0C
Default Value: 0x1B
Access: Read/write
Function: This 8-bit MMR represents the frequency at which the serial peripheral interface is operating. For more information on the
calculation of the baud rate, see the SCLK (Serial Clock I/O Pin) section.
SPI Receive Register
Name: SPIRX
Address: 0xFFFF0A04
Default Value: 0x00
Access: Read only
Function: This 8-bit MMR contains the data received via the serial peripheral interface.
SPI Transmit Register
Name: SPITX
Address: 0xFFFF0A08
Default Value: 0x00
Access: Write only
Function: This 8-bit MMR is written to, to transmit data via the serial peripheral interface.
Description
Reserved.
SPIRX Data Register Overflow Status Bit.
SPIRX Data Register IRQ.
SPIRX Data Register Full Status Bit.
SPITX Data Register Underflow Status Bit.
SPITX Data Register IRQ.
SPITX Data Register Empty Status Bit.
Set if SPIRX is overflowing.
Cleared by reading SPIRX register.
Set automatically if Bit 3 or Bit 5 is set.
Cleared by reading SPIRX register.
Set automatically if valid data is present in the SPIRX register.
Cleared by reading SPIRX register.
Set automatically if SPITX is underflowing.
Cleared by writing in the SPITX register.
Set automatically if Bit 0 is cleared or Bit 2 is set.
Cleared by writing in the SPITX register or, if transmission finished, by disabling the SPI.
Set by writing to SPITX to send data. This bit is set during transmission of data.
Cleared when SPITX is empty.
Rev.0 | Page 101 of 116
ADuC7032-8L
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