EVAL-ADUC7032QSPZ Analog Devices Inc, EVAL-ADUC7032QSPZ Datasheet - Page 6
![EVAL DEV QUICK START ADUC7032](/photos/9/24/92482/eval-aduc7032qspz_sml.jpg)
EVAL-ADUC7032QSPZ
Manufacturer Part Number
EVAL-ADUC7032QSPZ
Description
EVAL DEV QUICK START ADUC7032
Manufacturer
Analog Devices Inc
Series
QuickStart™ PLUS Kitr
Type
MCUr
Datasheet
1.EVAL-ADUC7032QSPZ.pdf
(116 pages)
Specifications of EVAL-ADUC7032QSPZ
Contents
Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
For Use With/related Products
ADuC7032
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 6 of 116
- Download datasheet (3Mb)
ADuC7032-8L
Parameter
LIN I/O GENERAL
LIN v.1.3 SPECIFICATION
LIN 2.0 SPECIFICATION
Baud Rate
VDD
Input Capacitance
LIN Comparator Response
I
I
I
I
V
V
V
V
V
V
V
VBAT Shift
GND Shift
R
V
Transmit Propagation Delay
Symmetry of Transmit
Symmetry of Receive
t
D1
D2
LIN DOM MAX
LIN_PAS_REC
LIN_PAS_DOM
LIN_NO_GND
dV
SYM
dV
LIN_DOM
LIN_REC
LIN_CNT
HYS
LIN_DOM_DRV_LOSUP
LIN_DOM_DRV_HISUP
LIN_RECESSIVE
SLAVE
SERIAL DIODE
dt
dt
Time
R
R
R
R
Propagation Delay
Receive Propagation Delay
Propagation Delay
1
1
L
L
L
L
1
500 Ω
1000 Ω
500 Ω
1000 Ω
1
1
1
1
1
30
1
30
30
30
1
1
1
1
1
1
Test Conditions/Comments
Supply voltage range at which the LIN interface is functional
Using 22 Ω resistor
Current limit for driver when LIN bus is in dominant state;
VBAT = VBAT(MAX)
Driver off; 7.0 V < V
Input leakage V
Control unit disconnected from ground,
GND = VDD; 0 V < V
LIN receiver dominant state, VDD > 7.0 V
LIN receiver recessive state, VDD > 7.0 V
LIN receiver center voltage, VDD > 7.0 V
LIN receiver hysteresis voltage
LIN dominant output voltage; VDD = 7.0 V
LIN dominant output voltage; VDD = 18 V
LIN recessive output voltage
Slave termination resistance
Voltage drop at the serial diode, D
V
Bus load conditions (C
1 nF||1 kΩ; 6.8 nF||660 Ω; 10 nF||500 Ω
V
V
V
Bus load conditions (C
1 nF||1 kΩ ; 6.8 nF||660 Ω; 10 nF||500 Ω
Slew rate
Slew rate
Bus load conditions ( C
1 nF||1 kΩ; 6.8 nF||660 Ω; 10 nF||500 Ω
Duty Cycle 1
Duty Cycle 2
DDMIN
DDMIN
DDMIN
DDMIN
TH
TH
V
D1 = t
TH
TH
V
D2 = t
Dominant and recessive edges, VBAT = 18 V
Dominant and recessive edges, VBAT = 7 V
Symmetry of rising and falling edge, VBAT = 18 V
Symmetry of rising and falling edge, VBAT = 7 V
SUP
SUP
REC(MAX)
DOM(MAX)
REC(MIN)
DOM(MIN)
= 7 V
= 7 V
= 7 V
= 7 V
= 7.0 V…18 V; t
= 7.0 V…18 V; t
BUS_REC(MIN)
BUS_REC(MAX)
= 0.284 × VBAT,
= 0.744 × VBAT,
= 0.422 × VBAT,
= 0.581 × VBAT,
LIN
/(2 × t
= 0 V
/(2 × t
BUS
LIN
< 18 V; VDD = V
< 18 V; VBAT = 12 V
BUS
BUS
BIT
BIT
BUS
BIT
BIT
= 50 μs,
= 50 μs,
||R
||R
||R
)
)
BUS
BUS
BUS
):
):
):
Rev.0 | Page 6 of 116
Ser_Int
LIN
− 0.7 V
Min
1000
7
40
−20
−1
−1
0.6 VDD
0.475 VDD
0.6
0.8
0.8 VDD
0
0
20
0.4
−2
−2
1
0.5
−5
−4
0.396
Typ
5.5
38
0.5 VDD
29
0.7
2
20,000
18
90
200
+20
+1
0.4 VDD
0.525 VDD
0.175 VDD
1.2
2
0.1 VDD
0.1 VDD
47
1
4
+2
6
+2
3
3
+5
+4
0.581
Max
Unit
Bits/sec
V
pF
μs
mA
μA
mA
mA
V
V
V
V
V
V
V
V
V
V
V
kΩ
V
μs
μs
μs
μs
V/μs
V/μs
μs
μs
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