EVAL-ADUC7032QSPZ Analog Devices Inc, EVAL-ADUC7032QSPZ Datasheet - Page 77
![EVAL DEV QUICK START ADUC7032](/photos/9/24/92482/eval-aduc7032qspz_sml.jpg)
EVAL-ADUC7032QSPZ
Manufacturer Part Number
EVAL-ADUC7032QSPZ
Description
EVAL DEV QUICK START ADUC7032
Manufacturer
Analog Devices Inc
Series
QuickStart™ PLUS Kitr
Type
MCUr
Datasheet
1.EVAL-ADUC7032QSPZ.pdf
(116 pages)
Specifications of EVAL-ADUC7032QSPZ
Contents
Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
For Use With/related Products
ADuC7032
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 77 of 116
- Download datasheet (3Mb)
GENERAL-PURPOSE I/O
The ADuC7032-8L features nine general-purpose bidirectional
I/O pins (GPIO). In general, many of the GPIO pins have multiple
functions that can be configured by user code. By default, the
GPIO pins are configured in GPIO mode. All GPIO pins have
an internal pull-up resistor, their sink capability is 0.8 mA, and
they can source 0.1 mA.
The nine GPIOs are grouped into three ports: Port0, Port1, and
Port2. Port0 is five bits wide. Port1 and Port2 are both two bits
wide. The GPIO assignment within each port is shown in Table 58.
A typical GPIO structure is shown in Figure 34.
External interrupts are present on GPIO_0, GPIO_5, GPIO_7,
and GPIO_8. These interrupts are level triggered and are active
high. These interrupts are not latched; therefore, the interrupts
source must be present until either IRQSTA or FIQSTA is
interrogated.
OUTPUT DRIVE ENABLE
1
ONLY AVAILABLE ON GPIO_0, GPIO_5, GPIO_7, AND GPIO_8.
GPxDAT[31:24]
GPxDAT[23:16]
OUTPUT DATA
GPxDAT[7:0]
INPUT DATA
GPIO IRQ
Figure 34. ADuC7032-8L GPIO
Rev.0 | Page 77 of 116
1
The interrupt source must be active for at least one CD-divided
core clock to guarantee recognition.
All port pins are configured and controlled by four sets (one set
for each port) of four port-specific MMRs.
•
•
•
•
where x corresponds to the port number (0, 1, or 2).
During normal operation, user code can control the function
and state of the external GPIO pins via these general-purpose
registers. All GPIO pins retain their external high or low during
power-down (POWCON) mode.
REG_DVDD
GPxCON: Portx control register
GPxDAT: Portx configuration and data register
GPxSET: Portx data set
GPxCLR: Portx data clear
GPIO
ADuC7032-8L
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