EVAL-ADUC7032QSPZ Analog Devices Inc, EVAL-ADUC7032QSPZ Datasheet - Page 76
![EVAL DEV QUICK START ADUC7032](/photos/9/24/92482/eval-aduc7032qspz_sml.jpg)
EVAL-ADUC7032QSPZ
Manufacturer Part Number
EVAL-ADUC7032QSPZ
Description
EVAL DEV QUICK START ADUC7032
Manufacturer
Analog Devices Inc
Series
QuickStart™ PLUS Kitr
Type
MCUr
Datasheet
1.EVAL-ADUC7032QSPZ.pdf
(116 pages)
Specifications of EVAL-ADUC7032QSPZ
Contents
Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
For Use With/related Products
ADuC7032
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 76 of 116
- Download datasheet (3Mb)
ADuC7032-8L
Timer3 Control Register
Name: T3CON
Address: 0xFFFF0368
Default Value: 0x0000
Access: Read/write once only
Function: This 16-bit MMR configures the mode of operation of Timer3, as shown in Table 57.
Table 57. T3CON MMR Bit Designations
Bit
15 to 9
8
7
6
5
4
3 to 2
1
0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Count Up/Count Down Enable.
Timer3 Enable.
Timer3 Operating Mode.
Watchdog Timer Mode Enable.
Reserved. This bit is reserved and should be written as 0 by user code.
Timer3 Clock (32.768 kHz) Prescalar.
Watchdog Timer IRQ Enable.
PD_OFF.
Set by user code to configure Timer3 to count up.
Cleared by user code to configure Timer3 to count down.
Set by user code to enable Timer3.
Cleared by user code to disable Timer3.
Set by user code to configure Timer3 to operate in periodic mode.
Cleared by user to configure Timer3 to operate in free-running mode.
Set by user code to enable watchdog mode.
Cleared by user code to disable watchdog mode.
Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0.
Cleared by user code to disable the IRQ option.
Set by user code to stop Timer3 when the peripherals are powered down via Bit 4 in the POWCON MMR.
Cleared by user code to enable Timer3 when the peripherals are powered down via Bit 4 in the POWCON MMR.
00 = source clock/1 (default).
01 = source clock/16.
10 = source clock/256.
11 = reserved.
Rev.0 | Page 76 of 116
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