EVAL-ADUC7032QSPZ Analog Devices Inc, EVAL-ADUC7032QSPZ Datasheet - Page 8

• Manufacturer Part Number: EVAL-ADUC7032QSPZ
• Description: EVAL DEV QUICK START ADUC7032
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCUr

Specifications of EVAL-ADUC7032QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• For Use With/related Products: ADuC7032
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7032-8L
TIMING SPECIFICATIONS
SPI Timing Specifications
Table 2. SPI Master Mode Timing (PHASE Mode = 1)
Parameter
t
t
t
t
t
t
t
t
t
1
2
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
t
t
HCLK
UCLK
depends on the clock divider or CD bits in PLLCON MMR. t
= 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
(POLARITY = 0)
(POLARITY = 1)
Description
SCLK low pulse width
SCLK high pulse width
Data output valid after SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
SCLK
SCLK
MOSI
MISO
1
1
t
DAV
t
SH
Figure 2. SPI Master Mode Timing (PHASE Mode = 1)
t
DSU
HCLK
2
MSB IN
= t
2
MSB
t
UCLK
DHD
t
SL
/2
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CD
t
.
DF
Min
0
3 × t
t
DR
BITS[6:1]
UCLK
BITS[6:1]
3.5
3.5
3.5
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
3.5
t
SR
HCLK
HCLK
t
LSB IN
SF
LSB
Max
(2 × t
UCLK
) + (2 × t
HCLK
)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns