EVAL-ADUC7032QSPZ Analog Devices Inc, EVAL-ADUC7032QSPZ Datasheet - Page 38

• Manufacturer Part Number: EVAL-ADUC7032QSPZ
• Description: EVAL DEV QUICK START ADUC7032
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCUr

Specifications of EVAL-ADUC7032QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• For Use With/related Products: ADuC7032
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7032-8L
16-BIT, SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERS
The ADuC7032-8L incorporates three independent Σ-Δ
analog-to-digital converters (ADCs), namely, the current
channel ADC (I-ADC), the voltage channel ADC (V-ADC),
and the temperature channel ADC (T-ADC). These precision
measurement channels integrate on-chip buffering; programmable
gain amplifiers; 16-bit, Σ-Δ modulators; and digital filtering and
are intended for the precision measurement of current, voltage,
and temperature variables in 12 V automotive battery systems.
CURRENT CHANNEL ADC (I-ADC)
This ADC is intended to convert battery current sensed through
an external 100 μΩ shunt resistor. On-chip programmable gain
means that the I-ADC can be configured to accommodate battery
current levels from ±1 A to ±1500 A.
As shown in Figure 15, the I-ADC employs a Σ-Δ conversion
technique to realize 16 bits of no missing codes performance.
VREF/136
VREF/136 VOLTAGE INPUT.
GND
IIN+
IIN–
VOLTAGE SOURCE
ANALOG INPUT DIAGNOSTIC
REG_AVDD REG_AVDD
ANALOG INPUT
DIAGNOSTIC
TWO 50µA IIN+ AND IIN–
CURRENT SOURCES.
CURRENT SOURCES
ALTERNATELY REVERSED
CHOP
CONVERSION CYCLE.
PROGRAMMABLE
THE INPUTS ARE
ANALOG INPUT
THROUGH THE
CHOPPING
AMPLIFIER PRESENTS
THE Σ-Δ MODULATOR.
BUFFER AMPLIFIER
A HIGH IMPEDANCE
PGA
INPUT STAGE FOR
THE PGA DRIVING
REFERENCE ON THE VREF
TO THE ADC BY DEFAULT.
PRECISION REFERENCE
REFERENCE IS ROUTED
THE BUFFER
THE INTERNAL 5ppm/°C
PIN CAN ALSO BE
AN EXTERNAL
SELECTED.
BUF
RANGES FROM ±2.3mV TO
GAIN AMPLIFIER ALLOWS
±1.2V (INT VREF = +1.2V).
PROGRAMMABLE GAIN
THE PROGRAMMABLE
EIGHT BIPOLAR INPUT
REFERENCE
INTERNAL
MODULATOR
VREF
AMPLIFIER
Σ-Δ
Figure 15. Current ADC, Top Level Overview
Σ-Δ ADC
PROGRAMMABLE
DIGITAL FILTER
QUANTIZATION NOISE INTRODUCED
BY THE MODULATOR. THE UPDATE
FILTER ARE PROGRAMMABLE VIA
RATE AND BANDWIDTH OF THIS
BEFORE BEING PROVIDED AS
CALIBRATION COEFFICIENTS
THE SINC3 FILTER REMOVES
THE CONVERSION RESULT.
CYCLE OF WHICH REPRESENTS
THE OUTPUT WORD FROM
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THE DIGITAL FILTER, THE DUTY
THE MODULATOR PROVIDES A
HIGH FREQUENCY 1-BIT DATA
WHICH IS ALSO CHOPPED) TO
THE SAMPLED ANALOG INPUT
DIGITAL COMPARATOR
THE DIGITAL FILTER IS
PRESET THRESHOLD.
STREAM (THE OUTPUT OF
THE ADC RESULT IS
THE ADCFLT MMR.
OUTPUT SCALING
PROGRAMMABLE
COMPARED TO A
SCALED BY THE
DIGITAL FILTER
Σ-Δ MODULATOR
VOLTAGE.
COEFFICIENT
COEFFICIENT
OFFSET
GAIN
CHOP
The modulator converts the sampled input signal into a digital
pulse train, whose duty cycle contains the digital information.
A modified Sinc3 programmable low-pass filter is then employed
to decimate the modulator output data stream to give a valid 16-bit
data conversion result at programmable output rates from 4 Hz
to 8 kHz in normal mode and 1 Hz to 2 kHz in low power mode.
The I-ADC also incorporates counter, comparator, and accu-
mulator logic. This allows the I-ADC result to generate an interrupt
after a predefined number of conversions has elapsed or if the
I-ADC result exceeds a programmable threshold value. A fast
ADC overrange feature is also supported. Once enabled, a 32-bit
accumulator automatically sums the 16-bit I-ADC results.
The time to a first valid (fully settled) result on the current channel
is three ADC conversion cycles with chop mode turned off and
two ADC conversion cycles with chop mode turned on.
THRESHOLD
NO MISSING CODES.
ENSURES 16 BITS
AVERAGE
ARCHITECTURE
OUTPUT
OUTPUT
FORMAT
RESULT
ADC
ADC
Σ-Δ ADC
THE Σ-Δ
GENERATES AN INTERRUPT
ADC RESULT<THRESHOLD.
ON COUNTER OVERFLOW.
COUNTS DOWN/RESET IF
RESULTS>THRESHOLD;
THRESHOLD COUNTER
THE FILTER IS SUMMED AND
AS PART OF THE CHOPPING
DATA-WORD OUTPUT FROM
COUNTS UP IF ADC
IMPLEMENTATION, EACH
AVERAGED WITH ITS
OUTPUT AVERAGE
PREDECESSOR.
INTERRUPT IF THE CURRENT
ACCUMULATOR
ADC FAST OVERRANGE
ADC RESULT
ADC RESULT
THRESHOLD
GENERATES AN ADC
INPUT IS GROSSLY
COUNTER
COUNTER
RESULT
OVERRANGED.
ADC
GENERATES AN INTERRUPT
ON COUNTER OVERFLOW.
COUNTS ADC RESULTS,
ADC RESULT COUNTER
GENERATES AN ADC
ADC ACCUMULATOR
ACCUMULATES THE
RESULT FROM ANY
ADC INTERRUPT
ONE OF FOUR
ADC RESULT.
GENERATOR
SOURCES.
ADC
INTERRUPT