EVAL-ADUC7032QSPZ Analog Devices Inc, EVAL-ADUC7032QSPZ Datasheet - Page 63

• Manufacturer Part Number: EVAL-ADUC7032QSPZ
• Description: EVAL DEV QUICK START ADUC7032
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCUr

Specifications of EVAL-ADUC7032QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• For Use With/related Products: ADuC7032
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWCON Prewrite Key POWKEY0
Name: POWKEY0
Address: 0xFFFF0404
Access: Write only
Key: 0x00000001
Function: POWCON is a keyed register that requires a 32-bit
key value to be written before and after POWCON. POWKEY0
is the prewrite key.
POWCON Postwrite Key POWKEY1
Name: POWKEY1
Address: 0xFFFF040C
Access: Write only
Key: 0x000000F4
Function: POWCON is a keyed register that requires a 32-bit
key value to be written before and after POWCON. POWKEY1
is the postwrite key.
Table 47. POWCON MMR Bit Designations
Bit
31 to 8
7
6
5
4
3
2 to 0
1
2
3
Timer peripherals are powered down if driven from the PLL output clock. Timers driven from an active clock source stay in normal power mode.
The peripherals that are powered down by this bit are as follows: SRAM, Flash/EE memory, and GPIO interfaces; and SPI and UART serial ports.
If user code powers down the MCU, a dummy MCU cycle should be included after the power-down command is written to POWCON.
Description
Reserved.
Precision 131 kHz Input Enable.
XTAL Power-Down.
PLL Power-Down.
Peripherals Power-Down.
Core Power-Down.
CD Core Clock Divider Bits.
Cleared by the user to power down the precision 131 kHz input enable.
Set by the user to enable the precision 131 kHz input enable. The precision 131 kHz oscillator must also be enabled via
HVCFG0[6]. Setting this bit increases current consumption by approximately 50 μA and should be disabled when not in use.
Cleared by the user to power down the external crystal circuitry.
Set by the user to enable the external crystal circuitry.
This bit is cleared to 0 to power-down the PLL. The PLL cannot be powered down if either the core or peripherals are enabled.
Bit 3, Bit 4, and Bit 5 must be cleared simultaneously.
Set by default, and set by hardware on a wake-up event.
Cleared to power-down the peripherals. The peripherals cannot be powered down if the core is enabled: Bit 3 and Bit 4 must
be cleared simultaneously. LIN can still respond to wake-up events even if this bit is cleared. The wake-up timer (Timer2) can
remain active if driven from a low power oscillator, even if this bit is cleared.
Set by default, and/or by hardware, on a wake-up event.
Cleared to power-down the ARM core.
Set by default, and set by hardware on a wake-up event.
000 = 20.48 MHz, 48.83 ns
001 = 10.24 MHz, 97.66 ns
010 = 5.12 MHz, 195.31 ns
011 = 2.56 MHz, 390.63 ns
100 = 1.28 MHz, 781.25 ns
101 = 640 kHz, 1.56 μs
110 = 320 kHz, 3.125 μs
111 = 160 kHz, 6.25 μs
1
3
2
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POWCON Register
Name: POWCON
Address: 0xFFFF0408
Default Value: 0x079
Access: Read/write
Function: This 8-bit register allows user code to dynamically
enter various low power modes and modify the CD divider that
controls the speed of the ARM7TDMI core.
ADuC7032-8L