EVAL-ADUC7032QSPZ Analog Devices Inc, EVAL-ADUC7032QSPZ Datasheet - Page 70
![EVAL DEV QUICK START ADUC7032](/photos/9/24/92482/eval-aduc7032qspz_sml.jpg)
EVAL-ADUC7032QSPZ
Manufacturer Part Number
EVAL-ADUC7032QSPZ
Description
EVAL DEV QUICK START ADUC7032
Manufacturer
Analog Devices Inc
Series
QuickStart™ PLUS Kitr
Type
MCUr
Datasheet
1.EVAL-ADUC7032QSPZ.pdf
(116 pages)
Specifications of EVAL-ADUC7032QSPZ
Contents
Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
For Use With/related Products
ADuC7032
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 70 of 116
- Download datasheet (3Mb)
ADuC7032-8L
Timer0 Value Register
Name: T0VAL0/T0VAL1
Address: 0xFFFF0304, 0xFFFF0308
Default Value: 0x0000, 0x00000000
Access: Read only
Function: These are 16-bit and 32-bit registers that hold the
16 least significant bits and 32 most significant bits, respectively.
T0VAL0 and T0VAL1 are read only. In 16-bit mode, 16-bit
T0VAL0 is used. In 48-bit mode, both 16-bit T0VAL0 and
32-bit T0VAL1 are used.
Timer0 Capture Register
Name: T0CAP
Address: 0xFFFF0314
Default Value: 0x0000
Access: Read/write
Function: This 16-bit register holds the 16-bit value captured
by an enabled IRQ event. It is available only in 16-bit mode.
Table 54. T0CON MMR Bit Designations
Bit
31 to 18
17
16 to 12
11
10 to 9
8
7
6
5
4
3 to 0
Description
Reserved. This bit is reserved and should be written as 0 by user code.
Event Select Range, 0 to 31. The events are described in Table 53.
Reserved. This bit is reserved and should be written as 0 by user code.
Clock Select.
Timer0 Enable Bit.
Timer0 Mode.
Reserved. This bit is reserved and should be written as 0 by user code.
Timer0 Mode of Operation.
Prescalar.
Event Select Bit.
Count Up. Available only in 16-bit mode.
0000 = source clock/1 (default).
0100 = source clock/16.
1000 = source clock/256.
1111 = source clock/32,768.
Set by the user to enable time capture of an event.
Cleared by the user to disable time capture of an event.
00 = core clock (default).
01 = low power 32.768 kHz oscillator.
10 = external 32.768 kHz watch crystal.
11 = precision 32.768 kHz oscillator.
Set by user for Timer0 to count up.
Cleared by user for Timer0 to count down (default).
Set by user to enable Timer0.
Cleared by user to disable Timer0 (default).
Set by user to operate in periodic mode.
Cleared by user to operate in free running mode (default).
0 = 16-bit operation (default).
1 = 48-bit operation.
Rev.0 | Page 70 of 116
Timer0 Control Register
Name: T0CON
Address: 0xFFFF030C
Default Value: 0x00000000
Access: Read/write
Function: This 32-bit MMR configures the mode of operation
of Timer0.
Timer0 Load Register
Name: T0LD
Address: 0xFFFF0300
Default Value: 0x0000
Access: Write once only
Function: This 16-bit register holds the 16-bit value that is
loaded into the counter. It is available only in 16-bit mode.
Timer0 Clear Register
Name: T0CLRI
Address: 0xFFFF0310
Access: Write only
Function: This 8-bit, write-only MMR is written (with any
value) by user code to refresh (reload) Timer0.
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