C8051F350-TB Silicon Laboratories Inc, C8051F350-TB Datasheet
C8051F350-TB
Specifications of C8051F350-TB
Related parts for C8051F350-TB
C8051F350-TB Summary of contents
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... Timer 0 + Timer 1 - Timer 2 VOLTAGE Timer 3 COMPARATOR 24.5 MHz PRECISION INTERNAL OSCILLATOR WITH CLOCK MULTIPLIER HIGH-SPEED CONTROLLER CORE 8 kB 8051 CPU (50 MIPS) DEBUG CIRCUITRY Copyright © 2007 by Silicon Laboratories C8051F350/1/2 ISP Flash MCU Family Port 0 Port 1 P2.0 768 B SRAM POR WDT C8051F35x ...
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... C8051F350/1/2 OTES 2 Rev. 1.1 ...
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... Current Mode DACS (IDA0 and IDA1).......................................................... 67 6.1. IDAC Output Scheduling................................................................................... 68 6.1.1. Update Output On-Demand ..................................................................... 68 6.1.2. Update Output Based on Timer Overflow ................................................ 68 6.1.3. Update Output Based on CNVSTR Edge................................................. 68 6.2. IDAC Output Mapping....................................................................................... 68 6.3. IDAC External Pin Connections ........................................................................ 71 7. Voltage Reference .................................................................................................. 73 8. Temperature Sensor............................................................................................... 77 C8051F350/1/2/3 Rev. 1.1 3 ...
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... C8051F350/1/2/3 9. Comparator0 ........................................................................................................... 79 9.1. Comparator0 Inputs and Outputs...................................................................... 83 10. CIP-51 Microcontroller ........................................................................................... 87 10.1.Instruction Set................................................................................................... 89 10.1.1.Instruction and CPU Timing ..................................................................... 89 10.1.2.MOVX Instruction and Program Memory ................................................. 89 10.2.Register Descriptions ....................................................................................... 93 10.3.Power Management Modes.............................................................................. 96 10.3.1.Idle Mode ................................................................................................. 96 10.3.2.Stop Mode................................................................................................ 96 11. Memory Organization and SFRs ........................................................................... 99 11.1.Program Memory.............................................................................................. 99 11.2.Data Memory .................................................................................................. 100 11.3.General Purpose Registers ............................................................................ 100 11 ...
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... Out, Slave In (MOSI).................................................................. 182 21.1.2.Master In, Slave Out (MISO).................................................................. 182 21.1.3.Serial Clock (SCK) ................................................................................. 182 21.1.4.Slave Select (NSS) ................................................................................ 182 21.2.SPI0 Master Mode Operation ......................................................................... 183 21.3.SPI0 Slave Mode Operation ........................................................................... 185 21.4.SPI0 Interrupt Sources ................................................................................... 185 21.5.Serial Clock Timing......................................................................................... 186 21.6.SPI Special Function Registers ...................................................................... 186 C8051F350/1/2/3 Rev. 1.1 5 ...
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... C8051F350/1/2/3 22. Timers.................................................................................................................... 195 22.1.Timer 0 and Timer 1 ....................................................................................... 195 22.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 195 22.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 196 22.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 197 22.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 198 22.2.Timer 2 .......................................................................................................... 203 22.2.1.16-bit Timer with Auto-Reload................................................................ 203 22.2.2.8-bit Timers with Auto-Reload................................................................ 204 22.3.Timer 3 .......................................................................................................... 207 22 ...
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... List of Figures 1. System Overview Figure 1.1. C8051F350 Block Diagram .................................................................... 19 Figure 1.2. C8051F351 Block Diagram .................................................................... 19 Figure 1.3. C8051F352 Block Diagram .................................................................... 20 Figure 1.4. C8051F353 Block Diagram .................................................................... 20 Figure 1.5. Development/In-System Debug Diagram............................................... 22 Figure 1.6. Memory Map .......................................................................................... 23 Figure 1.7. ADC0 Block Diagram ............................................................................. 24 Figure 1.8. IDAC Block Diagram .............................................................................. 25 Figure 1 ...
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... C8051F350/1/2/3 11. Memory Organization and SFRs Figure 11.1. Memory Map ........................................................................................ 99 12. Interrupt Handler 13. Prefetch Engine 14. Reset Sources Figure 14.1. Reset Sources.................................................................................... 115 Figure 14.2. Power-On and VDD Monitor Reset Timing ........................................ 116 15. Flash Memory Figure 15.1. Flash Memory Map............................................................................. 123 16. External RAM 17. Oscillators Figure 17 ...
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... Figure 23.8. PCA 8-Bit PWM Mode Diagram ......................................................... 218 Figure 23.9. PCA 16-Bit PWM Mode...................................................................... 219 Figure 23.10. PCA Module 2 with Watchdog Timer Enabled ................................. 220 24. Revision Specific Behavior Figure 24.1. Reading Package Marking ................................................................. 227 25. C2 Interface Figure 25.1. Typical C2 Pin Sharing....................................................................... 231 C8051F350/1/2/3 Rev. 1.1 9 ...
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... C8051F350/1/2 OTES 10 Rev. 1.1 ...
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... Table 1.1. Product Selection Guide ......................................................................... 18 2. Absolute Maximum Ratings 3. Global DC Electrical Characteristics 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F350/1/2/3 ................................................. 31 Table 4.2. LQFP-32 Package Dimensions .............................................................. 36 Table 4.3. QFN-28 Package Dimensions ................................................................ 16-Bit Analog to Digital Converter (ADC0) Table 5.1. ADC0 Unipolar Output Word Coding (AD0POL = 0) .............................. 47 Table 5.2. ADC0 Bipolar Output Word Coding (AD0POL = 1) ................................ 47 Table 5.3. ADC0 SINC3 Filter Typical RMS Noise (µ ...
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... C8051F350/1/2/3 Table 20.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator ............................................................... 178 Table 20.2. Timer Settings for Standard Baud Rates Using an External 25.0 MHz Oscillator ............................................... 178 Table 20.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator ......................................... 179 Table 20 ...
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... SFR Definition 12.1. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 SFR Definition 12.2. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SFR Definition 12.3. EIE1: Extended Interrupt Enable 109 SFR Definition 12.4. EIP1: Extended Interrupt Priority 110 SFR Definition 12.5. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . 112 SFR Definition 13.1. PFE0CN: Prefetch Engine Control . . . . . . . . . . . . . . . . . . . . . . 113 C8051F350/1/2/3 Rev. 1.1 13 ...
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... C8051F350/1/2/3 SFR Definition 14.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . 117 SFR Definition 14.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 SFR Definition 15.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 125 SFR Definition 15.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SFR Definition 15.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SFR Definition 16 ...
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... SFR Definition 23.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 226 C2 Register Definition 25.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 C2 Register Definition 25.2. DEVICEID: C2 Device 229 C2 Register Definition 25.3. REVID: C2 Revision 230 C2 Register Definition 25.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 230 C2 Register Definition 25.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 230 C8051F350/1/2/3 Rev. 1.1 15 ...
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... C8051F350/1/2 OTES 16 Rev. 1.1 ...
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... Each device is specified for 2.7 to 3.6 V operation over the industrial temperature range (–45 to +85 °C). The Port I/O and /RST pins are tolerant of input signals The C8051F350/1/2/3 are available in 28-pin QFN (also referred to as MLP or MLF) or 32-pin LQFP packaging, as shown in Figure 1.1 through Figure 1 ...
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... C8051F350/1/2/3 Table 1.1. Product Selection Guide C8051F350- 768 C8051F351- 768 C8051F352- 768 C8051F353- 768 — — — — Rev. 1.1 LQFP-32 QFN-28 LQFP-32 QFN-28 ...
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... AIN0 AIN1 Offset DAC AIN2 A AIN3 + Buffer PGA M + AIN4 U X AIN5 AIN6 Temp AIN7 Sensor Figure 1.1. C8051F350 Block Diagram Digital Power VDD GND Analog AV+ Power C2D AGND Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit 24.5 MHz 2% Clock ...
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... C8051F350/1/2/3 Digital Power VDD GND Analog AV+ Power C2D AGND Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit 24.5 MHz 2% Clock Internal Multiplier Oscillator VREF+ VREF– AIN0 AIN1 Offset AIN2 A + AIN3 Buffer PGA M + AIN4 U X AIN5 AIN6 Temp AIN7 Sensor Figure 1 ...
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... Number of Instructions 26 1.1.3. Additional Features The C8051F350/1/2/3 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. An extended interrupt handler allows the numerous analog and digital peripherals to operate indepen- dently of the controller core and interrupt the controller only when necessary. By requiring less intervention from the microcontroller core, an interrupt-driven system is more efficient and allows for easier implemen- tation of multi-tasking, real-time systems ...
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... All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping breakpoint in order to keep them synchronized. The C8051F350DK development kit provides all the hardware and software necessary to develop applica- tion code and perform in-circuit debugging with the C8051F35x MCUs. The kit includes software with a developer's studio and debugger debug adapter, a target application board with the associated MCU installed, and the required cables and wall-mount power supply ...
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... PROGRAM/DATA MEMORY (Flash) 0x1FFF RESERVED 0x1E00 0x1DFF 8 kB Flash (In-System Programmable in 512 Byte Sectors) 0x0000 C8051F350/1/2/3 DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE 0xFF Upper 128 RAM (Indirect Addressing Only) 0x80 0x7F (Direct and Indirect Addressing) 0x30 ...
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... C8051F350/1/2/3 1. 16-Bit Analog to Digital Converter (ADC0) The C8051F350/1/2/3 include a fully-differential, 24-bit (C8051F350/1) or 16-bit (C8051F352/3) Sigma- Delta Analog to Digital Converter (ADC) with on-chip calibration capabiliites. Two separate decimation fil- ters can be programmed for throughputs kHz. An internal 2.5 V reference is available differ- ential external reference can be used for ratiometric measurements. A Programmable Gain Amplifier (PGA) is included, with eight gain settings up to 128x ...
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... Two 8-bit Current-Mode DACs The C8051F350/1/2/3 devices include two 8-bit current-mode Digital-to-Analog Converters (IDACs). The maximum current output of the IDACs can be adjusted for four different current settings; 0.25 mA, 0.5 mA, 1 mA, and 2 mA. A flexible output update mechanism allows for seamless full-scale changes, and supports jitter-free updates for waveform generation ...
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... Serial Ports The C8051F350/1/2/3 Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hard- ware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. ...
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... Port Input/Output C8051F350/1/2/3 devices include 17 I/O pins. Port pins are organized as two byte-wide ports and one 1-bit port. The port pins behave like typical 8051 ports with a few enhancements. Each port pin can be config- ured as a digital or analog I/O pin. Pins selected as digital I/O can be configured for push-pull or open-drain operation. The “ ...
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... C8051F350/1/2/3 1.9. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. The counter/timer is driven by a programmable timebase that ...
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... Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. C8051F350/1/2/3 Min –55 –65 – ...
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... C8051F350/1/2/3 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter 1 Analog Supply Voltage Analog Supply Current Analog Supply Current with analog sub-systems inactive Analog-to-Digital Supply Delta (|V – AV+|) DD Digital Supply Voltage Digital Supply Current with CPU ...
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... Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F350/1/2/3 Pin Numbers Name ‘F350 ‘F351 ‘F352 ‘F353 DGND AGND 9 5 /RST 12 8 C2CK P2. C2D P0 P0 P0. XTAL1 P0. XTAL2 P0 P0 C8051F350/1/2/3 Type Description Power Digital Supply Voltage. Must be tied to +2 +3.6 V power ...
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... C8051F350/1/2/3 Table 4.1. Pin Definitions for the C8051F350/1/2/3 (Continued) Pin Numbers Name ‘F350 ‘F351 ‘F352 ‘F353 P0. CNVSTR P0 P1. AIN0.4 P1. AIN0.5 P1. AIN0.6 P1. AIN0 P1. IDA0 P1. IDA1 32 Type Description D I/O or Port 0.6. See Port I/O Section for a complete description External Convert Start Input for IDACs (See IDAC Section for complete description) ...
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... ADC0 Input Channel 4 (C8051F350/2 - See ADC0 Section for complete description). ADC0 Input Channel 5 (C8051F350/2 - See ADC0 Section for complete description). ADC0 Input Channel 6 (C8051F350/2 - See ADC0 Section for complete description). ADC0 Input Channel 7 (C8051F350/2 - See ADC0 Section for complete description). VREF Positive Voltage Pin (See VREF Section for complete description) ...
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... C8051F350/1/2/3 AIN0.0 1 AIN0 AIN0.2 4 AIN0.3 AIN0.4 5 AIN0 AIN0.6 8 AIN0.7 Figure 4.1. LQFP-32 Pinout Diagram (Top View) 34 C8051F350 C8051F352 Top View Rev. 1.1 24 P1.1 23 P1.0 22 DGND 21 VDD 20 P0.7 19 P0.6 18 P0.5 17 P0.4 ...
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... GND AIN0.0 1 AIN0.1 2 AIN0.2 3 AIN0.3 4 AGND 5 AV+ 6 P2.0 / C2D 7 Figure 4.2. QFN-28 Pinout Diagram (Top View) C8051F350/1/2/3 C8051F351 C8051F353 Top View GND Rev. 1.1 21 P1.2 / AIN0.6 20 P1.1 / AIN0.5 19 P1.0 / AIN0.4 18 DGND 17 VDD 16 P0.7 15 P0.6 35 ...
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... C8051F350/1/2/3 Figure 4.3. LQFP-32 Package Diagram Table 4.2. LQFP-32 Package Dimensions MIN TYP MAX — — 1.60 0.05 — 0.15 1.35 1.40 1.45 0.30 0.37 0.45 0.09 — 0.20 — 9.00 — — 7.00 — — 0.80 — — 9.00 — ...
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... Figure 4.4. QFN-28 Package Drawing Table 4.3. QFN-28 Package Dimensions MM MIN TYP A 0.80 0.90 A1 0.03 0.07 A3 0.25 REF b 0.18 0.25 D 5.00 BSC. D2 2.90 3.15 e 0.50 BSC. E 5.00 BSC. E2 2.90 3.15 L 0.45 0.55 Rev. 1.1 C8051F350/1/2/3 MAX 1.00 0.11 0.30 3.35 3.35 0.65 37 ...
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... C8051F350/1/2/3 Figure 4.5. Typical QFN-28 Landing Diagram 38 Rev. 1.1 ...
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... Figure 4.6. Typical QFN-28 Solder Paste Diagram Rev. 1.1 C8051F350/1/2/3 39 ...
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... C8051F350/1/2 OTES 40 Rev. 1.1 ...
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... Analog to Digital Converter (ADC0) The C8051F350/1/2/3 include a fully-differential, 24-bit (C8051F350/1) or 16-bit (C8051F352/3) Sigma- Delta Analog to Digital Converter (ADC) with on-chip calibration capabiliites. Two separate decimation fil- ters can be programmed for throughputs kHz. An internal reference is available differential external reference can be used for ratiometric measurements. A Programmable Gain Amplifier (PGA) is included, with eight gain settings up to 128x ...
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... C8051F350/1/2/3 5.1. Configuration ADC0 is enabled by setting the AD0EN bit in register ADC0MD (SFR Definition 5.3) to ‘1’. When the ADC is disabled placed in a low-power shutdown mode with all clocks turned off, to minimize unnecessary power consumption. The ADC will retain all of its settings in shutdown mode, with the exception of the AD0SM bits, which are reset to 000b (Idle Mode) ...
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... SFR Definition 5.6. Higher decimation ratios will produce lower-noise results over a longer conver- sion period. The minimum decimation ratio is 20. When using the fast filter output, the decimation ratio must be set to a multiple of 8. C8051F350/1/2/3 Bypass Buffer High Buffer+ ...
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... C8051F350/1/2/3 5.2. Calibrating the ADC ADC0 can be calibrated in-system for both gain and offset, using internal or system calibration modes. To ensure calibration accuracy, offset calibrations must be performed prior to gain calibrations not neces- sary to perform both internal and system calibrations system calibration will also compensate for any internal error sources ...
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... Example Decoding for Gain Register setting of 0x940000 (10010100 00000000 00000000b): 0 –5 –3 Slope Adjustment = 1.0 + 0.125 + 0.03125 = 1.15625 Figure 5.4. ADC0 Gain Calibration Register Coding C8051F350/1/2/3 24-bit ADC (C8051F350/1) ADC0COM 16-bit ADC (C8051F352/3) ADC0COM ...
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... C8051F350/1/2/3 5.3. Performing Conversions The ADC offers two conversion modes: Single Conversion, and Continuous Conversion. In single conver- sion mode, a single conversion result is produced for each of the filters (SINC3 and Fast). In continuous conversion mode, the ADC will perform back-to-back conversions until the ADC mode is changed. Proce- dures for single and continuous conversion modes are detailed in the sections below ...
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... Table 5.1. ADC0 Unipolar Output Word Coding (AD0POL = 0) Input Voltage* (AIN+ – AIN–) 24-bit Output Word (C8051F350/1) 16-bit Output Word (C8051F352/3) VREF – 1 LSB VREF / 2 +1 LSB 0 *Note: Input Voltage is voltage at ADC inputs after amplification by the PGA. Table 5.2. ADC0 Bipolar Output Word Coding (AD0POL = 1) Input Voltage* (AIN+ – ...
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... C8051F350/1/2/3 SFR Definition 5.1. ADC0CN: ADC0 Control — — — Bit7 Bit6 Bit5 Bits 7–5: Unused: Read = 000b, Write = don’t care. Bit 4: AD0POL: ADC0 Polarity. 0: ADC operates in Unipolar mode (straight binary result). 1: ADC operates in Bipolar mode (2's compliment result). Bit 3: AD0BCE: ADC0 Burnout Current Source Enable ...
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... ADC0 uses the internal VREF (2.5 V). Setting this bit to ‘0’ enables the internal Voltage Reference. 1: ADC0 uses an external VREF. Bits 1–0: Unused: Read = 00b, Write = don’t care. This SFR can only be modified when ADC0 is in IDLE mode. C8051F350/1/2/3 R/W R R/W R — ...
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... C8051F350/1/2/3 SFR Definition 5.3. ADC0MD: ADC0 Mode R/W R R/W AD0EN — Reserved Reserved Bit7 Bit6 Bit5 Bit 7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC is in low-power shutdown. 1: ADC0 Enabled. ADC is active and ready to perform calibrations or conversions. Note: Disabling the ADC automatically resets the AD0SM bits back to the "Idle" state. ...
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... This register contains the high bits of the 11-bit ADC Decimation Ratio. The decimation ratio determines the output word rate of ADC0, based on the Modulator Clock (MDCLK). See the ADC0DECL register description for more information. This SFR can only be modified when ADC0 is in IDLE mode. C8051F350/1/2/3 R/W R/W R/W ...
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... C8051F350/1/2/3 SFR Definition 5.6. ADC0DECL: ADC0 Decimation Ratio Register Low Byte R/W R/W R/W DECI7 DECI6 DECI5 Bit7 Bit6 Bit5 Bits 7–0: DECI[7:0]: ADC0 Decimation Ratio Register, Bits 7–0. This register contains the low byte of the 11-bit ADC Decimation Ratio. The decimation ratio determines the number of modulator input samples used to generate a single output word from the ADC ...
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... Negative Channel Low Input Buffer Enabled. Bits 1–0: AD0BNS: Negative Channel Input Selection Bypass Input Buffer (default Select Low Input Buffer Range Select High Input Buffer Range Reserved. This SFR can only be modified when ADC0 is in IDLE mode. C8051F350/1/2/3 R/W R/W R/W R/W AD0BNHE AD0BNLE Bit4 ...
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... C8051F350/1/2/3 SFR Definition 5.9. ADC0STA: ADC0 Status R R R/W AD0BUSY AD0CBSY AD0INT Bit7 Bit6 Bit5 Bit 7: AD0BUSY: ADC0 Conversion In-Progress Flag. 0: ADC0 is not performing conversions. 1: ADC0 conversion in progress. Bit 6: AD0CBSY: ADC0 Calibration In-Progress Flag. 0: ADC0 is not performing a calibration. 1: ADC0 calibration in progress. ...
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... R/W R/W R/W OCAL7 OCAL6 OCAL5 Bit7 Bit6 Bit5 Bits 7–0: OCAL[7:0]: ADC0 Offset Calibration Register Low Byte. This register contains the low byte of the 24-bit ADC Offset Calibration Value. C8051F350/1/2/3 R/W R/W R/W OCAL19 OCAL18 OCAL17 Bit4 Bit3 Bit2 R/W ...
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... C8051F350/1/2/3 SFR Definition 5.13. ADC0CGH: ADC0 Gain Calibration Register High Byte R/W R/W R/W GCAL23 GCAL22 GCAL21 Bit7 Bit6 Bit5 Bits 7–0: GCAL[23:16]: ADC0 Gain Calibration Register High Byte. This register contains the high byte of the 24-bit ADC Gain Calibration Value. ...
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... R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: ADC0L: ADC0 Conversion Register (SINC3 Filter) Low Byte. C8051F350/1: This register contains bits 7–0 of the 24-bit ADC SINC3 filter conversion result. C8051F352/3: This register contains all zeros (00000000b). C8051F350/1/2/3 R/W R/W R/W R/W ...
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... R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: ADC0FL: ADC0 Conversion Register (Fast Filter) Low Byte. C8051F350/1: This register contains bits 7–0 of the 24-bit ADC fast filter conversion result. C8051F352/3: This register contains all zeros (00000000b). 58 R/W R/W R/W R/W ADC0FH ...
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... The temperature sensor is automatically enabled when it is selected with the ADC multi- plexer. See Section “8. Temperature Sensor’ on page 77 for more details on the temperature sensor. Temp+ Temperature Sensor Temp- Figure 5.5. ADC0 Multiplexer Connections C8051F350/1/2/3 ADC0MUX AIN0.0 AIN0.1 AIN0.2 AIN0.3 AIN0.4 AIN0 ...
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... C8051F350/1/2/3 SFR Definition 5.22. ADC0MUX: ADC0 Analog Multiplexer Control R/W R/W R/W AD0PSEL Bit7 Bit6 Bit5 Bits 7–4: AD0PSEL: ADC0 Positive Multiplexer Channel Select. 0000 = AIN0.0 0001 = AIN0.1 0010 = AIN0.2 0011 = AIN0.3 0100 = AIN0.4 0101 = AIN0.5 0110 = AIN0.6 0111 = AIN0.7 1111 = Temperature Sensor All Other Settings = AGND Bits 3– ...
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... Table 5.3. ADC0 Electrical Characteristics V = AV+ = 3.0 V, VREF = 2.5 V External, PGA Gain = 1, MDCLK = 2.4576 MHz, DD Decimation Ratio = 1920, –40 to +85 °C unless otherwise noted. Parameter 24-bit ADC (C8051F350/1) Resolution No Missing Codes 16-bit ADC (C8051F352/3) Resolution No Missing Codes All Devices Integral Nonlinearity Offset Error (Calibrated) Offset Drift vs ...
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... C8051F350/1/2/3 Table 5.3. ADC0 Electrical Characteristics (Continued AV+ = 3.0 V, VREF = 2.5 V External, PGA Gain = 1, MDCLK = 2.4576 MHz, DD Decimation Ratio = 1920, –40 to +85 °C unless otherwise noted. Parameter Power Specifications AV+ Supply Current to ADC0 AV+ Supply Current to Input Buffers (Each Enabled Buffer) Power Supply Rejection Table 5.4. ADC0 SINC3 Filter Typical RMS Noise (µ ...
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... Hz 6.99 Notes: 1. Flicker-free (Noise-free) Resolution = V REF where Full Input Range = -------------------------- - PGA Gain 2. Output Word Rate assuming Modular Clock frequency = 2.4576 MHz (sampling clock frequency = 19.2 kHz) C8051F350/1/2/3 in Unipolar Mode (bits) PGA Gain Setting 19.95 19.81 19.54 19.31 19.22 19.06 18 ...
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... C8051F350/1/2/3 Table 5.7. ADC0 Fast Filter Typical RMS Noise (µV) Decimation Output Word Ratio Rate* 1920 10 Hz 4.84 768 25 Hz 17.92 640 30 Hz 29.98 384 50 Hz 103.93 320 60 Hz 171.12 192 100 Hz 550.29 305.55 140.58 *Note: Output Word Rate assuming Modulator Clock frequency = 2.4576 MHz (sampling clock frequency = 19 ...
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... Hz 9.43 Notes: 1. Flicker-free (Noise-free) Resolution = V REF where Full Input Range = -------------------------- - PGA Gain 2. Output Word Rate assuming Modular Clock frequency = 2.4576 MHz (sampling clock frequency = 19.2 kHz) C8051F350/1/2/3 in Unipolar Mode (bits) PGA Gain Setting 16.11 15.90 15.49 14.95 14.24 13 ...
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... C8051F350/1/2 OTES 66 Rev. 1.1 ...
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... Current Mode DACS (IDA0 and IDA1) The C8051F350/1/2/3 devices include two 8-bit current-mode Digital-to-Analog Converters (IDACs). The maximum current output of the IDACs can be adjusted for four different current settings; 0.25 mA, 0.5 mA, 1 mA, and 2 mA. The IDACs can be individually enabled or disabled using the enable bits in the corre- sponding IDAC Control Register (IDA0CN or IDA1CN) ...
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... C8051F350/1/2/3 6.1. IDAC Output Scheduling A flexible output update mechanism allows for seamless full-scale changes and supports jitter-free updates for waveform generation. Three update modes are provided, allowing IDAC output updates on a write to the IDAC’s data register Timer overflow external pin edge. ...
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... SFR Definition 6.2. IDA0: IDA0 Data Word R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: IDA0 Data Word Bits. Bits 7–0 hold the 8-bit IDA0 Data Word. C8051F350/1/2/3 R/W R/W R R/W IDA0CSC — Bit4 Bit3 Bit2 Bit1 ...
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... C8051F350/1/2/3 SFR Definition 6.3. IDA1CN: IDA1 Control R/W R/W R/W IDA1EN IDA1CM Bit7 Bit6 Bit5 Bit 7: IDA1EN: IDA1 Enable. 0: IDA1 Disabled. 1: IDA1 Enabled. Bits 6–4: IDA1CM[2:0]: IDA1 Update Source Select bits. 000: DAC output updates on Timer 0 overflow. 001: DAC output updates on Timer 1 overflow. ...
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... IDAC output. When using the IDACs, the IDAC pins should be skipped in the Crossbar by setting the corresponding PnSKIP bits to a ‘1’. Figure 6.3 shows the pin connections for IDA0 and IDA1. IDA0 IDA1 Figure 6.3. IDAC Pin Connections C8051F350/1/2/3 IDA0EN 0 P1.6 1 ...
Page 72
... C8051F350/1/2/3 . Table 6.1. IDAC Electrical Characteristics –40 to +85 ° 3.0 V Full-scale output current set unless otherwise specified. DD Parameter Static Performance Resolution Integral Nonlinearity Differential Nonlinearity Output Compliance Range Output Noise Offset Error Full Scale Output Gain-Error Tempco VDD Power Supply Rejection ...
Page 73
... Voltage Reference There are two voltage reference options for the C8051F350/1/2/3 ADCs: the internal 2.5 V reference volt- age external reference voltage (see Figure 7.1). The AD0VREF bit in the ADC0CF register selects the reference source. The internal voltage reference circuit consists of a 1.25 V, temperature stable bandgap voltage reference generator and a gain-of-two output buffer amplifier, to produce a 2.5 V voltage reference. When the inter- nal voltage reference is used driven out on the VREF+ pin. In this configuration, the VREF– ...
Page 74
... C8051F350/1/2/3 SFR Definition 7.1. REF0CN: Reference Control — — — Bit7 Bit6 Bit5 NOTE: Modification of this register is not necessary in most applications. The appropriate circuitry is enabled when it is needed by a peripheral. Bits7–2: Unused. Read = 000000b; Write = don’t care. Bit1: BIASE: Internal Oscillator Bias Enable. ...
Page 75
... VREF–) Voltage on VREF+ or VREF– pin with respect to AGND Input Current Common Mode Rejection Ratio Power Specifications Internal Reference Bias and Band Gap Generator C8051F350/1/2/3 Conditions Min 25 °C ambient 2.35 To AGND To AV+ Load = 0 to 200 µA to AGND 4.7 µF tantalum, 0.1 µF ceramic bypass capacitors 0.1 µ ...
Page 76
... C8051F350/1/2 OTES 76 Rev. 1.1 ...
Page 77
... The two channels are connected to the ADC inputs internally, using the ADC’s ana- log multiplexer. The temperature sensor system can be used in single-ended or differential mode to measure the temperature of the C8051F350/1/2/3. Single channel measurements produce more output voltage per degree C, but are not as linear as differential measurements. See Table 8.1 for temperature sensor electrical characteristics ...
Page 78
... C8051F350/1/2/3 -50 Figure 8.2. Single Channel Transfer Function -50 Figure 8.3. Differential Transfer Function (Slope x Temp ) + Offset TEMP C Temp = (V - Offset) / Slope C TEMP Offset ( Celsius) Slope (V / deg Temperature (Celsius) Slope (V / deg C) Offset ( Celsius (Slope x Temp ) + Offset TEMP C Temp = (V - Offset) / Slope C TEMP 0 50 Temperature (Celsius) Rev ...
Page 79
... Comparator0 C8051F350/1/2/3 devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 9.1. The Comparator offers programmable response time and hysteresis and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 asynchronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is not active. This allows the Comparator to operate and generate an output with the device in STOP mode. When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull (see Section “ ...
Page 80
... C8051F350/1/2/3 CP0+ VIN+ + CP0 CP0- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled Figure 9.2. Comparator Hysteresis Plot The Comparator hysteresis is software-programmable via its Comparator Control register CPT0CN. The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. The Comparator hysteresis is programmed using Bits3– ...
Page 81
... Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. Bits1–0: CP0HYN1–0: Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. C8051F350/1/2/3 R/W R/W R/W CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000 Bit4 Bit3 Bit2 Rev ...
Page 82
... C8051F350/1/2/3 SFR Definition 9.2. CPT0MD: Comparator0 Mode Selection R R R/W — — CP0RIE Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 Rising-edge interrupt disabled. 1: Comparator0 Rising-edge interrupt enabled. Bit4: CP0FIE: Comparator0 Falling-Edge Interrupt Enable. ...
Page 83
... P1.4. The CP0 output (synchronized to SYSCLK) is available at P1.5 when it is enabled with bit 4 in the XBR0 register. P0.0 P0.2 P0.4 P0.6 P1.0 P1.2 P1.4 P1.6 P0.1 P0.3 P0.5 P0.7 P1.1 P1.3 P1.5 P1.7 Figure 9.3. Comparator Pin Connections C8051F350/1/2/3 XBR0 VDD CP0 + + SET SET CP0 - - Q Q CLR CLR (SYNCHRONIZER) GND CPT0MX Rev ...
Page 84
... C8051F350/1/2/3 SFR Definition 9.3. CPT0MX: Comparator0 MUX Selection R/W R/W R/W CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3 CMX0P2 CMX0P1 Bit7 Bit6 Bit5 Bits7–4: CMX0N3–CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the Comparator0 negative input. ...
Page 85
... Input Bias Current Input Offset Voltage Power Supply Power Supply Rejection Power-up Time Supply Current at DC *Note: Vcm is the common-mode voltage on CP0+ and CP0–. C8051F350/1/2/3 Conditions Min CP0+ – CP0– = 100 mV — CP0+ – CP0– = –100 mV — CP0+ – CP0– = 100 mV — ...
Page 86
... C8051F350/1/2 OTES 86 Rev. 1.1 ...
Page 87
... DATA POINTER PC INCREMENTER PROGRAM COUNTER (PC) PRGM. ADDRESS REG. CONTROL RESET LOGIC CLOCK STOP POWER CONTROL IDLE Figure 10.1. CIP-51 Block Diagram C8051F350/1/2/3 - Extended Interrupt Handler - Reset Input - Power Management Modes - Integrated Debug Logic DATA BUS B REGISTER TMP1 TMP2 SRAM ADDRESS ALU ...
Page 88
... C8051F350/1/2/3 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles ...
Page 89
... Subtract indirect RAM from A with borrow SUBB A, #data Subtract immediate from A with borrow INC A Increment A INC Rn Increment register INC direct Increment direct byte INC @Ri Increment indirect RAM DEC A Decrement A DEC Rn Decrement register C8051F350/1/2/3 Description Arithmetic Operations Rev. 1.1 Clock Bytes Cycles ...
Page 90
... C8051F350/1/2/3 Table 10.1. CIP-51 Instruction Set Summary (Continued) Mnemonic DEC direct Decrement direct byte DEC @Ri Decrement indirect RAM INC DPTR Increment Data Pointer MUL AB Multiply A and B DIV AB Divide Decimal adjust A ANL A, Rn AND Register to A ANL A, direct AND direct byte to A ANL A, @Ri ...
Page 91
... Absolute jump LJMP addr16 Long jump SJMP rel Short jump (relative address) JMP @A+DPTR Jump indirect relative to DPTR JZ rel Jump if A equals zero JNZ rel Jump if A does not equal zero C8051F350/1/2/3 Description Boolean Manipulation Program Branching Rev. 1.1 Clock Bytes Cycles ...
Page 92
... C8051F350/1/2/3 Table 10.1. CIP-51 Instruction Set Summary (Continued) Mnemonic CJNE A, direct, rel Compare direct byte to A and jump if not equal CJNE A, #data, rel Compare immediate to A and jump if not equal Compare immediate to Register and jump if not CJNE Rn, #data, rel equal Compare immediate to indirect and jump if not ...
Page 93
... SFR Definition 10.3. DPH: Data Pointer High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and Flash memory. C8051F350/1/2/3 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W ...
Page 94
... C8051F350/1/2/3 SFR Definition 10.4. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction cleared all other arithmetic operations. Bit6: AC: Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into (addition borrow from (subtraction) the high order nibble ...
Page 95
... This register is the accumulator for arithmetic operations. SFR Definition 10. Register R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7– Register. This register serves as a second accumulator for certain arithmetic operations. C8051F350/1/2/3 R/W R/W R/W R/W ACC.4 ACC.3 ACC.2 ACC.1 Bit4 Bit3 Bit2 R/W ...
Page 96
... C8051F350/1/2/3 10.3. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states ...
Page 97
... Writing a ‘1’ to this bit will place the CIP-51 into IDLE mode. This bit will always read ‘0’. 1: CIP-51 forced into IDLE mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, and all peripherals remain active.) C8051F350/1/2/3 R/W R/W R/W R/W — ...
Page 98
... C8051F350/1/2 OTES 98 Rev. 1.1 ...
Page 99
... Memory Organization and SFRs The memory organization of the C8051F350/1/2/3 is similar to that of a standard 8051. There are two sep- arate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. The memory map is shown in Figure 11.1. ...
Page 100
... C8051F350/1/2/3 11.2. Data Memory The C8051F350/1/2/3 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. ...
Page 101
... SCON0 SBUF0 ADC0DECL 90 P1 TMR3CN TMR3RLL TMR3RLH 88 TCON TMOD TL0 DPL 0(8) 1(9) 2(A) (bit addressable) C8051F350/1/2/3 ADC0CF ADC0FL ADC0FM ADC0MD ADC0CN PFE0CN IT01CF IDA1 P0SKIP P1SKIP TMR2L TMR2H ADC0L ADC0M ADC0H OSCICL ADC0CGL ADC0CGM ADC0CGH SPI0DAT P0MDOUT P1MDOUT P2MDOUT ADC0DEC ...
Page 102
... C8051F350/1/2/3 Table 11.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description ACC 0xE0 Accumulator ADC0BUF 0xBD ADC0 Buffer Control ADC0CF 0xFB ADC0 Configuration ADC0CGH 0xAD ADC0 Gain Calibration High ADC0CGL 0xAB ADC0 Gain Calibration Low ...
Page 103
... SPI Clock Rate Control SPI0CN 0xF8 SPI Control SPI0DAT 0xA3 SPI Data TCON 0x88 Timer/Counter Control TH0 0x8C Timer/Counter 0 High TH1 0x8D Timer/Counter 1 High C8051F350/1/2/3 Rev. 1.1 Page 130 130 134 145 145 146 146 147 147 148 148 149 149 ...
Page 104
... C8051F350/1/2/3 Table 11.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description TL0 0x8A Timer/Counter 0 Low TL1 0x8B Timer/Counter 1 Low TMOD 0x89 Timer/Counter Mode TMR2CN 0xC8 Timer/Counter 2 Control TMR2H 0xCD Timer/Counter 2 High ...
Page 105
... Therefore, the fastest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL C8051F350/1/2/3 Rev. 1.1 105 ...
Page 106
... C8051F350/1/2/3 is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR ...
Page 107
... Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. Bit 0: EX0: Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the /INT0 input. C8051F350/1/2/3 R/W R/W R/W R/W ES0 ET1 ...
Page 108
... C8051F350/1/2/3 SFR Definition 12.2. IP: Interrupt Priority R R/W R/W — PSPI0 PT2 Bit7 Bit6 Bit5 Bit 7: UNUSED. Read = 1, Write = don't care. Bit 6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. ...
Page 109
... Enable interrupt requests generated by the AD0INT flag. Bits 2–1: RESERVED. Read = 00. Must Write 00. Bit 0: ESMB0: Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. C8051F350/1/2/3 R/W R/W R/W EPCA0 EADC0 Reserved Reserved ...
Page 110
... C8051F350/1/2/3 SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PT3 Reserved PCP0 Bit7 Bit6 Bit5 Bit 7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set to high priority level. ...
Page 111
... IN1PL); the flag remains logic 0 while the input is inac- tive. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. C8051F350/1/2/3 IT1 IN1PL /INT1 Interrupt ...
Page 112
... C8051F350/1/2/3 SFR Definition 12.5. IT01CF: INT0/INT1 Configuration R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to SFR Definition 22.1 for INT0/1 edge- or level-sensitive interrupt selection. Bit 7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 input is active high. Bits 6–4: IN1SL2–0: /INT1 Port Pin Selection Bits These bits select which Port pin is assigned to /INT1. Note that this pin assignment is inde- pendent of the Crossbar ...
Page 113
... Prefetch Engine The C8051F350/1/2/3 family of devices incorporate a 2-byte prefetch engine. Because the access time of the Flash memory is 40 ns, and the minimum instruction time is 20 ns, the prefetch engine is necessary for full-speed code execution. Instructions are read from Flash memory two bytes at a time by the prefetch engine, and given to the CIP-51 processor core to execute ...
Page 114
... C8051F350/1/2 OTES 114 Rev. 1.1 ...
Page 115
... Comparator 0 Px Px.x C0RSEF Missing Clock Detector (one- shot) EN System Clock CIP-51 Microcontroller Core Extended Interrupt Handler Figure 14.1. Reset Sources C8051F350/1/2/3 VDD Power On Reset Supply Monitor + '0' - Enable PCA (Software Reset) WDT SWRSF EN FLASH Operation System Reset Rev. 1.1 /RST (wired-OR) ...
Page 116
... C8051F350/1/2/3 14.1. Power-On Reset During power-up, the device is held in a reset state and the /RST pin is driven low until additional delay occurs before the device is released from reset; the delay decreases as the V V RST ramp time increases (V ramp time is defined as how fast V ...
Page 117
... DD This bit indicates the current power supply status ( below the above the Bits5–0: Reserved. Read = Variable. Write = don’t care. C8051F350/1/2/3 Monitor to drop below V DD monitor will still be disabled after the DD monitor as a reset source is shown below: DD monitor. DD Monitor Control ...
Page 118
... C8051F350/1/2/3 14.3. External Reset The external /RST pin provides a means for external circuitry to force the device into a reset state. Assert- ing an active-low signal on the /RST pin generates a reset; an external pull-up and/or decoupling of the /RST pin may be necessary to avoid erroneous noise-induced resets. See Table 14.1 for complete /RST pin specifications ...
Page 119
... Read: Last reset was not a power- reset source. 1: Read: Last reset was a power- Write: V monitor is a reset source. DD Bit0: PINRSF: HW Pin Reset Flag. 0: Source of last reset was not /RST pin. 1: Source of last reset was /RST pin. C8051F350/1/2/3 R/W R R/W R/W WDTRSF MCDRSF PORSF Bit4 Bit3 Bit2 Bit1 monitor reset ...
Page 120
... C8051F350/1/2/3 Table 14.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter /RST Output Low Voltage I OL /RST Input High Voltage /RST Input Low Voltage /RST Input Pullup Current V Monitor Threshold ( RST Time from last system clock rising Missing Clock Detector Timeout ...
Page 121
... Step 4. Write the first key code to FLKEY: 0xA5. Step 5. Write the second key code to FLKEY: 0xF1. Step 6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased. Step 7. Clear the PSWE and PSEE bits. Step 8. Re-enable interrupts. C8051F350/1/2/3 Rev. 1.1 Monitor DD 121 ...
Page 122
... C8051F350/1/2/3 15.1.3. Flash Write Procedure Bytes in Flash memory can be written one byte at a time groups of two. The FLBWE bit in register PFE0CN (SFR Definition 13.1) controls whether a single byte or a block of two bytes is written to Flash during a write operation. When FLBWE is cleared to ‘0’, the Flash will be written one byte at a time. When FLBWE is set to ‘ ...
Page 123
... Flash pages are locked Access limit set according to the Flash security lock byte Figure 15.1. Flash Memory Map C8051F350/1/2/3 11111101b 00000010b 3 (First two Flash pages + Lock Byte Page) 0x0000 to 0x03FF (first two Flash pages) and 0x1C00 to 0x1DFF (Lock Byte Page) ...
Page 124
... C8051F350/1/2/3 The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. Accessing Flash from the C2 debug interface: 1 ...
Page 125
... Flash by writing a non-0xA5 value to FLKEY from software. Read: When read, bits 1–0 indicate the current Flash lock state. 00: Flash is write/erase locked. 01: The first key code has been written (0xA5). 10: Flash is unlocked (writes/erases allowed). 11: Flash writes/erases disabled until the next reset. C8051F350/1/2 R/W — — ...
Page 126
... Bits3–0: RESERVED. Read = 0000b. Must Write 0000b. Table 15.1. Flash Electrical Characteristics V = 2.7 to 3.6 V; –40 to +85 ºC unless otherwise specified. DD Parameter Flash Size C8051F350/1/2/3 Endurance Erase Cycle Time 50 MHz System Clock Write Cycle Time 50 MHz System Clock *Note: 512 bytes at addresses 0x1E00 to 0x1FFF are reserved. ...
Page 127
... External RAM The C8051F350/1/2/3 devices include 512 bytes of RAM mapped into the external data memory space. All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the External Mem- ory Interface Control Register (EMI0CN as shown in SFR Definition 16 ...
Page 128
... C8051F350/1/2 OTES 128 Rev. 1.1 ...
Page 129
... All C8051F350/1/2/3 devices include a programmable internal oscillator that defaults as the system clock after a system reset. The internal oscillator period can be programmed via the OSCICL register, shown in SFR Definition 17.2. On C8051F350/1/2/3 devices, OSCICL is factory calibrated to obtain a 24.5 MHz fre- quency. Electrical specifications for the precision internal oscillator are given in Table 17.1 on page 136. Note that the system clock may be derived from the programmed internal oscillator divided defined by the IFCN bits in register OSCICN ...
Page 130
... R/W Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0. Write = don’t care. Bits 6–0: OSCICL: Internal Oscillator Calibration Register. This register determines the internal oscillator period. On C8051F350/1/2/3 devices, the reset value is factory calibrated to generate an internal oscillator frequency of 24.5 MHz. 130 R/W — ...
Page 131
... Step 2. Configure XTAL1 and XTAL2 as analog inputs. Step 3. Enable the external oscillator. Step 4. Wait at least 1 ms. Step 5. Poll for XTLVLD => ‘1’. Step 6. Switch the system clock to the external oscillator. Note: Tuning-fork crystals may require additional settling time before XTLVLD returns a valid result. C8051F350/1/2/3 Rev. 1.1 131 ...
Page 132
... C8051F350/1/2/3 The capacitors shown in the external crystal configuration provide the load capacitance required by the crystal for correct oscillation. These capacitors are “in series” as seen by the crystal and “in parallel” with the stray capacitance of the XTAL1 and XTAL2 pins. Note: The load capacitance depends upon the crystal and the manufacturer. Please refer to the crystal datasheet when completing these calculations ...
Page 133
... MHz = 3.0) Since the frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 17 22: 0.150 MHz = 3. 3 0.150 MHz C = 146 48.8 pF Therefore, the XFCN value to use in this example is 011b and pF. C8051F350/1/2/3 Rev. 1.1 = 3.0 V and DD 133 ...
Page 134
... C8051F350/1/2/3 SFR Definition 17.3. OSCXCN: External Oscillator Control R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal Oscillator is running and stable. Bits6–4: XOSCMD2–0: External Oscillator Mode Bits. ...
Page 135
... Clock Multiplier not ready. 1: Clock Multiplier ready (locked). Bits4–2: Unused. Read = 000b; Write = don’t care. Bits1–0: MULSEL: Clock Multiplier Input Select These bits select the clock supplied to the Clock Multiplier. MULSEL C8051F350/1/2/3 R/W R/W R/W R/W — — — Bit4 Bit3 ...
Page 136
... C8051F350/1/2/3 17.4. System Clock Selection The internal oscillator requires little start-up time and may be selected as the system clock immediately fol- lowing the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typ- ically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in register OSCXCN) is set to ‘ ...
Page 137
... CP0 Outputs 4 SPI 2 SMBus SYSCLK 4 PCA 2 Lowest T0, T1 Priority 8 P0 (P0.0-P0. (P1.0-P1.7) P2 Figure 18.1. Port I/O Functional Block Diagram C8051F350/1/2/3 XBR0, XBR1, PnMDOUT, PnSKIP Registers PnMDIN Registers Priority Decoder Digital Crossbar P0 8 I/O Cells P1 8 I/O Cells P2 I/O (P2.0) Cell Rev. 1.1 P0 ...
Page 138
... C8051F350/1/2/3 /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT Analog Select ANALOG INPUT PORT-INPUT Figure 18.2. Port I/O Cell Block Diagram 138 VDD VDD (WEAK) GND Rev. 1.1 PORT PAD ...
Page 139
... P0SKIP[0:7] Port pin potentially assignable to peripheral SF Signals Special Function Signals are not assigned by the crossbar. When these signals are enabled, the CrossBar must be manually configured to skip their corresponding port pins. Figure 18.3. Crossbar Priority Decoder with No Pins Skipped C8051F350/1/2 CNVSTR ...
Page 140
... C8051F350/1/2/3 SF Signals x1 x2 PIN I TX0 RX0 CP0A CP0 SCK MISO MOSI NSS* SDA SCL /SYSCLK CEX0 CEX1 CEX2 ECI P0SKIP[0:7] Port pin potentially assignable to peripheral SF Signals Special Function Signals are not assigned by the crossbar. When these signals are enabled, the CrossBar must be manually configured to skip their corresponding port pins ...
Page 141
... For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode Table. The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers are disabled while the Crossbar is disabled. C8051F350/1/2/3 Rev. 1.1 141 ...
Page 142
... C8051F350/1/2/3 SFR Definition 18.1. XBR0: Port I/O Crossbar Register R/W — — CP0AE Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP0AE: Comparator0 Asynchronous Output Enable 0: Asynchronous CP0 unavailable at Port pin. 1: Asynchronous CP0 routed to Port pin P1.4. ...
Page 143
... Unused. Read = 0b. Write = don’t care. Bits1–0: PCA0ME: PCA Module I/O Enable Bits. 00: All PCA I/O unavailable at Port pins. 01: CEX0 routed to Port pin. 10: CEX0, CEX1 routed to Port pins. 11: CEX0, CEX1, CEX2 routed to Port pins. C8051F350/1/2/3 R/W R/W R R/W T0E ECIE — ...
Page 144
... C8051F350/1/2/3 18.3. General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose I/O. Ports P0–P2 are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin ...
Page 145
... Bits7–0: Analog Input Configuration Bits for P0.7–P0.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P0.n pin is configured as an analog input. 1: Corresponding P0.n pin is not configured as an analog input. C8051F350/1/2/3 R/W R/W R/W R/W P0 ...
Page 146
... C8051F350/1/2/3 SFR Definition 18.5. P0MDOUT: Port0 Output Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in regis- ter P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. (Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of P0MDOUT) ...
Page 147
... Bits7–0: Analog Input Configuration Bits for P1.7–P1.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P1.n pin is configured as an analog input. 1: Corresponding P1.n pin is not configured as an analog input. C8051F350/1/2/3 R/W R/W R/W R/W P1 ...
Page 148
... C8051F350/1/2/3 SFR Definition 18.9. P1MDOUT: Port1 Output Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P1.7–P1.0 (respectively): ignored if corresponding bit in regis- ter P1MDIN is logic 0. 0: Corresponding P1.n Output is open-drain. 1: Corresponding P1.n Output is push-pull. SFR Definition 18.10. P1SKIP: Port1 Skip ...
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... SFR Definition 18.12. P2MDOUT: Port2 Output Mode — — — Bit7 Bit6 Bit5 Bits7–1: Unused. Read = 0000000b. Write = don’t care. Bit0: Output Configuration Bit for P2.0. 0: P2.0 Output is open-drain. 1: P2.0 Output is push-pull. C8051F350/1/2 — — — — Bit4 Bit3 Bit2 Bit1 R R ...
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... C8051F350/1/2/3 Table 18.1. Port I/O DC Electrical Characteristics V = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters I = –3 mA, Port I/O push-pull OH Output High Voltage I = –10 µA, Port I/O push-pull –10 mA, Port I/O push-pull OH Output Low Voltage Input High Voltage Input Low Voltage ...
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... SMBUS CONTROL LOGIC Arbitration Interrupt SCL Synchronization Request SCL Generation (Master Mode) SDA Control IRQ Generation 7 Figure 19.1. SMBus Block Diagram C8051F350/1/2 Overflow T1 Overflow 01 TMR2H Overflow 10 TMR2L Overflow 11 FILTER SCL N Control Data Path SDA Control Control SMB0DAT FILTER N Rev. 1.1 SCL ...
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... C8051F350/1/2/3 19.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: 1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. 2. The I2C-Bus Specification -- Version 2.0, Philips Semiconductor. 3. System Management Bus Specification -- Version 1.1, SBS Implementers Forum. ...
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... LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and no data is lost. C8051F350/1/2/3 R/W D7 D6-0 ...
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... C8051F350/1/2/3 19.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency ...
Page 155
... Timeout detection (SCL Low Timeout and/or Bus Free Timeout) • SDA setup and hold time extensions • Slave event enable/disable • Clock source selection These options are selected in the SMB0CF register, as described in Section “19.4.1. SMBus Configuration Register’ on page 156. C8051F350/1/2/3 Rev. 1.1 155 ...
Page 156
... C8051F350/1/2/3 19.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins ...
Page 157
... SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see Figure 19.4). When a Free Timeout is detected, the interface will respond STOP was detected (an interrupt will be generated, and STO will be set). C8051F350/1/2/3 T SCL High Timeout High Minimum SDA Hold Time – ...
Page 158
... C8051F350/1/2/3 SFR Definition 19.1. SMB0CF: SMBus Clock/Configuration R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly mon- itors the SDA and SCL pins. 0: SMBus interface disabled. 1: SMBus interface enabled. ...
Page 159
... Important note about the SI bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI. Table 19.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 19.4 for SMBus sta- tus decoding using the SMB0CN register. C8051F350/1/2/3 Rev. 1.1 159 ...
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... C8051F350/1/2/3 SFR Definition 19.2. SMB0CN: SMBus Control R R R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: SMBus operating in Master Mode. Bit6: TXMODE: SMBus Transmit Mode Indicator. ...
Page 161
... ACK/NACK received. SI • A byte has been received. • A START or repeated START followed by a slave address + R/W has been received. • A STOP has been received. C8051F350/1/2/3 Cleared by Hardware When: • A STOP is generated. • Arbitration is lost. • A START is detected. • Arbitration is lost. • SMB0DAT is not written before the start of an SMBus frame. • ...
Page 162
... C8051F350/1/2/3 19.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register ...
Page 163
... Notice that the ‘data byte transferred’ interrupts occur after the ACK cycle in this mode. S SLA Interrupt Received by SMBus Interface Transmitted by SMBus Interface Figure 19.5. Typical Master Transmitter Sequence C8051F350/1/2 Data Byte A Data Byte Interrupt Interrupt S = START P = STOP ...
Page 164
... C8051F350/1/2/3 19.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direc- tion bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial data. After each byte is received, ACKRQ is set to ‘ ...
Page 165
... Receiver sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode. S SLA W Interrupt Received by SMBus Interface Transmitted by SMBus Interface Figure 19.7. Typical Slave Receiver Sequence C8051F350/1/2/3 A Data Byte A Data Byte Interrupt Interrupt S = START P = STOP A = ACK W = WRITE SLA = Slave Address Rev ...
Page 166
... C8051F350/1/2/3 19.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received. Upon entering Slave Transmitter Mode, an interrupt is generated and the ACKRQ bit is set ...
Page 167
... NACK received. 1100 A master data or address byte was transmitted; ACK received. C8051F350/1/2/3 Typical Response Options Load slave address + R/W into SMB0DAT. Set STA to restart transfer. Abort transfer. Load next data byte into SMB0DAT. End transfer with STOP. End transfer with STOP and start another transfer ...
Page 168
... C8051F350/1/2/3 Table 19.4. SMBus Status Decoding (Continued) Values Read Current SMbus State A master data byte was received; 1000 ACK requested. A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. A Slave byte was transmitted error detected. A illegal STOP or bus error was ...
Page 169
... X STOP. A slave byte was received; ACK requested. 0000 Lost arbitration while transmitting data byte as master. C8051F350/1/2/3 Typical Response Options Acknowledge received address. Do not acknowledge received address. Acknowledge received address. Do not acknowledge received address. Reschedule failed transfer; do not acknowledge received address. Abort failed transfer. ...
Page 170
... C8051F350/1/2 OTES 170 Rev. 1.1 ...
Page 171
... UART0 interrupt (transmit complete or receive complete). Write to SBUF Stop Bit Start Tx Clock UART Baud Rate Generator Rx Clock Start Figure 20.1. UART0 Block Diagram C8051F350/1/2/3 SFR Bus TB8 SBUF SET (TX Shift CLR Zero Detector Shift ...
Page 172
... C8051F350/1/2/3 20.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 20.2), which is not user- accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. ...
Page 173
... RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. MARK START D0 D1 BIT SPACE BIT TIMES BIT SAMPLING Figure 20.4. 8-Bit UART Timing Diagram C8051F350/1/2/3 TX RS-232 RS-232 C8051Fxxx LEVEL RX XLTR ...
Page 174
... C8051F350/1/2/3 20.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg- ister PSW) for error detection, or used in multiprocessor communications ...
Page 175
... Master Slave Device Device Figure 20.6. UART Multi-Processor Mode Interconnect Diagram C8051F350/1/2/3 Slave Slave Device Device Rev. 1.1 V+ 175 ...
Page 176
... C8051F350/1/2/3 SFR Definition 20.1. SCON0: Serial Port 0 Control R/W R R/W S0MODE — MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. ...
Page 177
... This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmis- sion. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the con- tents of the receive latch. C8051F350/1/2/3 R/W R/W R/W ...
Page 178
... C8051F350/1/2/3 Table 20.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 –0.32% 115200 –0.32% 57600 0.15% 28800 –0.32% 14400 0.15% 9600 –0.32% 2400 –0.32% 1200 0.15% *Note: SCA1–SCA0 and T1M bit definitions can be found in Section 22.1. ...
Page 179
... SCA1–SCA0 and T1M bit definitions can be found in Section 22.1. C8051F350/1/2/3 Timer Clock SCA1–SCA0 T1M* Source (pre-scale select)* SYSCLK XX SYSCLK XX SYSCLK XX SYSCLK / 12 00 SYSCLK / 12 ...
Page 180
... C8051F350/1/2/3 Table 20.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% 115200 0.00% 57600 0 ...
Page 181
... SPI0CKR Clock Divide SYSCLK Logic Transmit Data Buffer Shift Register 7 6 Receive Data Buffer Write SPI0DAT SFR Bus Figure 21.1. SPI Block Diagram C8051F350/1/2/3 SFR Bus SPI0CFG SPI0CN SPI CONTROL LOGIC Data Path Pin Interface Control Control MOSI Tx Data SPI0DAT SCK ...
Page 182
... C8051F350/1/2/3 21.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 21.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operat- ing as a master and an input when SPI0 is operating as a slave ...
Page 183
... SPI device. In this mode, the output value of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-purpose I/O pins. Figure 21.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. C8051F350/1/2/3 Rev. 1.1 183 ...
Page 184
... C8051F350/1/2/3 Master Device 1 Figure 21.2. Multiple-Master Mode Connection Diagram Master Device Figure 21.3. 3-Wire Single Master and Slave Mode Connection Diagram Master Device GPIO Figure 21.4. 4-Wire Single Master and Slave Mode Connection Diagram 184 NSS GPIO MISO MISO Master MOSI ...
Page 185
... The new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte which caused the overrun is lost. C8051F350/1/2/3 Rev. 1.1 185 ...
Page 186
... C8051F350/1/2/3 21.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock ...
Page 187
... This bit will be set to logic 1 when the receive buffer has been read and contains no new information. If there is new information available in the receive buffer that has not been read, this bit will return to logic 0. NOTE: RXBMT = 1 when in Master Mode. *Note: See Table 21.1 for timing parameters. C8051F350/1/2/3 R CKPOL ...
Page 188
... C8051F350/1/2/3 SFR Definition 21.2. SPI0CN: SPI0 Control R/W R/W R/W SPIF WCOL MODF Bit7 Bit6 Bit5 Bit 7: SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared by hardware ...
Page 189
... SCK 2 SPI 0 CKR for 0 <= SPI0CKR <= 255 Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04, 2000000 ------------------------- - f = × SCK 200 kHz SCK C8051F350/1/2/3 R/W R/W R/W R/W SCR4 SCR3 SCR2 SCR1 Bit4 Bit3 Bit2 Bit1 ) + 1 Rev. 1.1 R/W Reset Value SCR0 00000000 Bit0 SFR Address: 0xA2 ...
Page 190
... C8051F350/1/2/3 SFR Definition 21.4. SPI0DAT: SPI0 Data R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: SPI0DAT: SPI0 Transmit and Receive Data. The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT places the data into the transmit buffer and initiates a transfer when in Master Mode. A read of SPI0DAT returns the contents of the receive buffer ...
Page 191
... SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 21.6. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MIS MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 21.7. SPI Master Timing (CKPHA = 1) C8051F350/1/2/3 T MCKL T T MIS MIH T MCKL T MIH Rev ...
Page 192
... C8051F350/1/2/3 NSS T SE SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 21.8. SPI Slave Timing (CKPHA = 0) NSS T SE SCK* T CKH T SIS MOSI T T SOH SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. ...
Page 193
... T SCK Low Time CKL T MOSI Valid to SCK Sample Edge SIS T SCK Sample Edge to MOSI Change SIH T SCK Shift Edge to MISO Change SOH *Note equal to one period of the device system clock (SYSCLK) in ns. SYSCLK C8051F350/1/2/3 Min SYSCLK SYSCLK SYSCLK SYSCLK — — ...
Page 194
... C8051F350/1/2 OTES 194 Rev. 1.1 ...
Page 195
... As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are enabled. C8051F350/1/2/3 Timer 2 Modes: 16-bit timer with auto-reload Two 8-bit timers with auto-reload Two 8-bit timers with auto-reload Rev ...
Page 196
... C8051F350/1/2/3 The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section “18.1. Priority Crossbar Decoder’ on page 139 for information on selecting and configuring external I/O pins) ...
Page 197
... IN0PL in register IT01CF (see Section “12.5. External Interrupts’ on page 111 for details on the external input signals /INT0 and /INT1). Pre-scaled Clock 0 SYSCLK 1 T0 Crossbar GATE0 IN0PL XOR /INT0 Figure 22.2. T0 Mode 2 Block Diagram C8051F350/1/2/3 CKCON TMOD IT01CF ...
Page 198
... C8051F350/1/2/3 22.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock ...
Page 199
... IT0: Interrupt 0 Type Select. This bit selects whether the configured /INT0 interrupt will be edge or level sensitive. /INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition 12.5). 0: /INT0 is level triggered. 1: /INT0 is edge triggered. C8051F350/1/2/3 R/W R/W R/W R/W TR0 ...
Page 200
... C8051F350/1/2/3 SFR Definition 22.2. TMOD: Timer Mode R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only when TR1 = 1 AND /INT1 is active as defined by bit IN1PL in regis- ter IT01CF (see SFR Definition 12 ...