C8051F350-TB Silicon Laboratories Inc, C8051F350-TB Datasheet - Page 27

• Manufacturer Part Number: C8051F350-TB
• Description: PROTOTYPINGBOARDWITH C8051F350
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F350-TB

• Contents: Board
• Processor To Be Evaluated: C8051F35x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F350
• Silicon Family Name: C8051F35x
• Kit Contents: Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F350
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.8.
C8051F350/1/2/3 devices include 17 I/O pins. Port pins are organized as two byte-wide ports and one 1-bit
port. The port pins behave like typical 8051 ports with a few enhancements. Each port pin can be config-
ured as a digital or analog I/O pin. Pins selected as digital I/O can be configured for push-pull or open-drain
operation. The “weak pull-ups” that are fixed on typical 8051 devices may be globally disabled to save
power.
The Digital Crossbar allows mapping of internal digital system resources to port I/O pins. On-chip
conter/timers, serial buses, hardware interrupts, and other digital signals can be configured to appear on
the port pins using the Crossbar control resgiters. This allows the user to select the exact mix of general-
purpose port I/O, digital, and analog resources needed for the application.
Highest
Lowest
Priority
Priority
Port Input/Output
SYSCLK
Outputs
SMBus
T0, T1
UART
P0
P1
P2
PCA
CP0
SPI
(P0.0-P0.7)
(P1.0-P1.7)
Figure 1.10. Port I/O Functional Block Diagram
2
2
4
2
4
2
8
8
(P2.0)
Rev. 1.1
PnSKIP Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
8
8
PnMDIN Registers
PnMDOUT,
C8051F350/1/2/3
Cells
Cells
Cell
I/O
I/O
I/O
P0
P1
P2
P0.0
P0.7
P1.0
P1.7
P2.0
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