C8051F350-TB Silicon Laboratories Inc, C8051F350-TB Datasheet - Page 42
C8051F350-TB
Manufacturer Part Number
C8051F350-TB
Description
PROTOTYPINGBOARDWITH C8051F350
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F350-TB
Contents
Board
Processor To Be Evaluated
C8051F35x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F350
Silicon Family Name
C8051F35x
Kit Contents
Board
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F350
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F350/1/2/3
5.1.
Configuration
ADC0 is enabled by setting the AD0EN bit in register ADC0MD (SFR Definition 5.3) to ‘1’. When the ADC
is disabled, it is placed in a low-power shutdown mode with all clocks turned off, to minimize unnecessary
power consumption. The ADC will retain all of its settings in shutdown mode, with the exception of the
AD0SM bits, which are reset to 000b (Idle Mode).
5.1.1. Voltage Reference Selection
The ADC’s voltage reference is selected using the AD0VREF bit in register ADC0CF (SFR Definition 5.2).
When set to ‘1’, the ADC uses an external voltage reference source. When cleared to ‘0’, the internal refer-
ence is used. A more detailed description of the voltage reference options can be found in Section
“7. Voltage Reference’ on page 73.
5.1.2. Analog Inputs
The ADC’s analog inputs are connected to external device pins or internal voltages as described in Section
“5.6. Analog Multiplexer’ on page 59. They can be configured as either single-ended (one independent
input measured with respect to AGND) or differential (two independent inputs measured with respect to
each other). For accurate measurements, the ADC inputs must remain within the input range specifications
found in Table 5.3. To prevent damage to the device, all external ADC inputs must also remain within the
Absolute Maximum ratings for the input pin, given in Table 2.1.
5.1.2.1. Programmable Gain Amplifier
A programmable gain amplifier (PGA) provides amplification settings of 1, 2, 4, 8, 16, 32, 64, and 128 for
the ADC inputs. The PGA gain setting is controlled by the AD0GN bits in register ADC0CN (SFR Definition
5.1).
5.1.2.2. Input Buffers
Independent input buffers are included for AIN+ and AIN–, as shown in Figure 5.2. Each input has a set of
two buffers that can be used to minimize the input current of the ADC for sensitive measurements. The
“low” input buffer can be used when the absolute pin input voltage is in the lower half of the supply range.
The “high” input buffer on each pin can be used when the absolute pin input voltage is in the upper half of
the supply range. See Table 5.3 for the input buffer range specifications. The input buffers can also be
bypassed, for a direct connection to the PGA inputs. The ADC input buffers are controlled with the
ADC0BUF register (SFR Definition 5.8).
42
Rev. 1.1
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