C8051F350-TB Silicon Laboratories Inc, C8051F350-TB Datasheet - Page 143

• Manufacturer Part Number: C8051F350-TB
• Description: PROTOTYPINGBOARDWITH C8051F350
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F350-TB

• Contents: Board
• Processor To Be Evaluated: C8051F35x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F350
• Silicon Family Name: C8051F35x
• Kit Contents: Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F350
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bits1–0: PCA0ME: PCA Module I/O Enable Bits.
WEAKPUD XBARE
R/W
Bit7
WEAKPUD: Port I/O Weak Pull-up Disable.
0: Weak Pull-ups enabled (except for Ports whose I/O are configured as analog input).
1: Weak Pull-ups disabled.
XBARE: Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
T1E: T1 Enable
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
T0E: T0 Enable
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
ECIE: PCA0 External Counter Input Enable
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
Unused. Read = 0b. Write = don’t care.
00: All PCA I/O unavailable at Port pins.
01: CEX0 routed to Port pin.
10: CEX0, CEX1 routed to Port pins.
11: CEX0, CEX1, CEX2 routed to Port pins.
SFR Definition 18.2. XBR1: Port I/O Crossbar Register 1
R/W
Bit6
T1E
R/W
Bit5
T0E
R/W
Bit4
Rev. 1.1
ECIE
R/W
Bit3
Bit2
—
R
C8051F350/1/2/3
R/W
Bit1
PCA0ME
SFR Address:
R/W
Bit0
0xE2
00000000
Reset Value
143